Lines Matching +full:map +full:- +full:to +full:- +full:dma +full:- +full:channel

1 /* SPDX-License-Identifier: GPL-2.0 */
2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
5  * Synopsys DesignWare AXI DMA Controller driver.
19 #include "../virt-dma.h"
33 	/* Register map for DMAX_NUM_CHANNELS <= 8 */
58 	struct dma_device	dma;  member
123 	return &dchan->dev->device;  in dchan2dev()
128 	return &chan->vc.chan.dev->device;  in chan2dev()
154 #define DMAC_CHEN		0x018 /* R/W DMAC Channel Enable */
155 #define DMAC_CHEN_L		0x018 /* R/W DMAC Channel Enable 00-31 */
156 #define DMAC_CHEN_H		0x01C /* R/W DMAC Channel Enable 32-63 */
157 #define DMAC_CHSUSPREG		0x020 /* R/W DMAC Channel Suspend */
158 #define DMAC_CHABORTREG		0x028 /* R/W DMAC Channel Abort */
166 /* DMA channel registers offset */
171 #define CH_CTL_L		0x018 /* R/W Chan Control 00-31 */
172 #define CH_CTL_H		0x01C /* R/W Chan Control 32-63 */
174 #define CH_CFG_L		0x020 /* R/W Chan Configuration 00-31 */
175 #define CH_CFG_H		0x024 /* R/W Chan Configuration 32-63 */
203 #define UNUSED_CHANNEL		0x3F /* Set unused DMA channel to 0x3F */
204 #define DMA_APB_HS_SEL_BIT_SIZE	0x08 /* HW handshake bits per channel */
207 #define DMA_REG_MAP_CH_REF	0x08 /* Channel count to choose register map */
332  * DW AXI DMA channel interrupts
336  * @DWAXIDMAC_IRQ_DMA_TRF: Dma transfer complete
350  * @DWAXIDMAC_IRQ_WR2RO_ERR: Slave Interface write to read only error
351  * @DWAXIDMAC_IRQ_RD2RWO_ERR: Slave Interface read to write only error
352  * @DWAXIDMAC_IRQ_WRONCHEN_ERR: Slave Interface write to channel error
357  * @DWAXIDMAC_IRQ_SUSPENDED: Channel Suspended Status
358  * @DWAXIDMAC_IRQ_DISABLED: Channel Disabled Status
359  * @DWAXIDMAC_IRQ_ABORTED: Channel Aborted Status