30  * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
52  *    which occur for the current LLI entry, and the DMAC raises TC at the
53  *    end of every LLI entry.  Observed behaviour shows the DMAC listening
59  *    zero).  The data is transferred from the current LLI entry, until
61  *    will then move to the next LLI entry. Unsupported by PL080S.
106  *	register and LLI word for transfer size.
145  * @reg_lli: transfer LLI address register
272  * @pool: a pool for the LLI descriptors
273  * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
276  * @lli_words: how many words are used in each LLI item for this variant
297 /* The order of words in an LLI. */
304 /* Total words in an LLI. */
309  * Number of LLIs in each LLI buffer allocated for one transfer
383  * pl08x_write_lli() - Write an LLI into the DMA controller.
386  * list containing the source, destination, control word and next LLI is
388  * SRC, DST, LLI and control registers. On FTDMAC020 also the SIZE
392 		struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg)  in pl08x_write_lli()  argument
398 			phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST],  in pl08x_write_lli()
399 			lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL],  in pl08x_write_lli()
400 			lli[PL080S_LLI_CCTL2], ccfg);  in pl08x_write_lli()
405 			phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST],  in pl08x_write_lli()
406 			lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], ccfg);  in pl08x_write_lli()
408 	writel_relaxed(lli[PL080_LLI_SRC], phychan->reg_src);  in pl08x_write_lli()
409 	writel_relaxed(lli[PL080_LLI_DST], phychan->reg_dst);  in pl08x_write_lli()
410 	writel_relaxed(lli[PL080_LLI_LLI], phychan->reg_lli);  in pl08x_write_lli()
413 	 * The FTMAC020 has a different layout in the CCTL word of the LLI  in pl08x_write_lli()
415 	 * Convert the LLI item CCTL into the proper values to write into  in pl08x_write_lli()
419 		u32 llictl = lli[PL080_LLI_CCTL];  in pl08x_write_lli()
429 		 * Bit 28: TC_MSK - mask on all except last LLI  in pl08x_write_lli()
458 		 * part the LLI, i.e. only gets written to the control  in pl08x_write_lli()
510 		writel_relaxed(lli[PL080_LLI_CCTL], phychan->reg_control);  in pl08x_write_lli()
515 		writel_relaxed(lli[PL080S_LLI_CCTL2],  in pl08x_write_lli()
522  * Set the initial DMA register values i.e. those for the first LLI
523  * The next LLI pointer and the configuration interrupt bit have
790 	 * Locate the next LLI - as this is an array,  in pl08x_getbytes_chan()
801 		 * A LLI pointer going backward terminates the LLI list  in pl08x_getbytes_chan()
963  * LLI handling
1166  * Fills in one LLI for a certain transfer descriptor and advance the counter
1178 	/* Advance the offset to next LLI. */  in pl08x_fill_lli_for_desc()
1223 			"lli", "", "csrc", "cdst", "clli", "cctl", "cctl2");  in pl08x_dump_lli()
1236 			"lli", "", "csrc", "cdst", "clli", "cctl");  in pl08x_dump_lli()
1325 		 *   Here, Obviously as DMA controller doesn't know when a lli's  in pl08x_fill_llis_for_desc()
1326 		 *   transfer gets over, it can't load next lli. So in this  in pl08x_fill_llis_for_desc()
1327 		 *   case, there has to be an assumption that only one lli is  in pl08x_fill_llis_for_desc()
1405 				"%s max bytes per lli = %zu\n",  in pl08x_fill_llis_for_desc()
1432 					"%s fill lli with single lli chunk of "  in pl08x_fill_llis_for_desc()
1458 				"%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",  in pl08x_fill_llis_for_desc()
1475 		/* Link back to the first LLI. */  in pl08x_fill_llis_for_desc()
1478 		/* The final LLI terminates the LLI. */  in pl08x_fill_llis_for_desc()
1480 		/* The final LLI element shall also fire an interrupt. */  in pl08x_fill_llis_for_desc()
1862 	 * the last LLI item by other code.  in pl08x_ftdmac020_memcpy_cctl()
2579 	if (of_property_read_bool(np, "lli-bus-interface-ahb1"))  in pl08x_of_probe()
2581 	if (of_property_read_bool(np, "lli-bus-interface-ahb2"))  in pl08x_of_probe()