Lines Matching +full:access +full:- +full:granularity
1 /* SPDX-License-Identifier: GPL-2.0-only */
22 * (port-driver, region-driver, nvdimm object-drivers... etc).
83 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) in eig_to_granularity() argument
86 return -EINVAL; in eig_to_granularity()
87 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; in eig_to_granularity()
91 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
99 *ways = 3 << (eiw - 8); in eiw_to_ways()
102 return -EINVAL; in eiw_to_ways()
108 static inline int granularity_to_eig(int granularity, u16 *eig) in granularity_to_eig() argument
110 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || in granularity_to_eig()
111 !is_power_of_2(granularity)) in granularity_to_eig()
112 return -EINVAL; in granularity_to_eig()
113 *eig = ilog2(granularity) - 8; in granularity_to_eig()
120 return -EINVAL; in ways_to_eiw()
126 return -EINVAL; in ways_to_eiw()
129 return -EINVAL; in ways_to_eiw()
178 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */
204 * Using struct_group() allows for per register-block-type helper routines,
205 * without requiring block-type agnostic code to include the prefix.
271 * struct cxl_register_map - DVSEC harvested register block mapping parameters
273 * @base: virtual base of the register-block-BAR + @block_offset
305 #define CXL_INSTANCES_COUNT -1
318 #define CXL_RESOURCE_NONE ((resource_size_t) -1)
347 #define CXL_QOS_CLASS_INVALID -1
350 * struct cxl_decoder - Common CXL HDM Decoder Attributes
359 * @commit: device/decoder-type specific callback to commit settings to hw
360 * @reset: device/decoder-type specific callback to reset hw settings
411 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder
415 * @mode: which memory type / access-mode-partition this decoder targets
429 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder
436 * come in two flavors, root-level decoders, statically defined by platform
437 * firmware, and mid-level decoders, where interleave-granularity,
438 * interleave-width, and the target list are mutable.
450 * struct cxl_root_decoder - Static platform CXL address decoder
453 * @hpa_to_spa: translate CXL host-physical-address to Platform system-physical-address
470 * enum cxl_config_state - State machine for region configuration
477 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware
488 * struct cxl_region_params - region settings
525 * struct cxl_region - CXL region
528 * @mode: Endpoint decoder allocation / access mode
534 * @coord: QoS access coordinates for the region
535 * @memory_notifier: notifier for setting the access coordinates to node
592 * struct cxl_port - logical collection of upstream port devices and
598 * @id: id for port device-name
608 * @dead: last ep has been removed, force port re-creation
639 * struct cxl_root - logical collection of root cxl_port items
664 return xa_load(&port->dports, (unsigned long)dport_dev); in cxl_find_dport_by_dev()
673 * struct cxl_dport - CXL downstream port
681 * @coord: access coordinates (bandwidth and latency performance attributes)
697 * struct cxl_ep - track an endpoint's interest in a port
710 * struct cxl_region_ref - track a region's interest in a port
732 * parent and their ->uport_dev / host device is out-of-line of the port
737 return port->uport_dev == port->dev.parent; in is_cxl_root()
758 DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev))
801 return cxl_decoder_autoremove(host, &cxlrd->cxlsd.cxld); in cxl_root_decoder_autoremove()
806 * struct cxl_endpoint_dvsec_info - Cached DVSEC info