Lines Matching full:bandwidth

36 	 * Scoped Latency and Bandwidth Information Structure in Coherent Device  in cdat_normalize()
598 * Transient context for containing the current calculation of bandwidth when
607 * cxl_endpoint_gather_bandwidth - collect all the endpoint bandwidth in an xarray
608 * @cxlr: CXL region for the bandwidth calculation
610 * @usp_xa: (output) the xarray that collects all the bandwidth coordinates
616 * Collects aggregated endpoint bandwidth and store the bandwidth in
618 * device. Each endpoint consists the minimum of the bandwidth from DSLBIS
619 * from the endpoint CDAT, the endpoint upstream link bandwidth, and the
620 * bandwidth from the SSLBIS of the switch CDAT for the switch upstream port to
680 /* Direct upstream link from EP bandwidth */ in cxl_endpoint_gather_bandwidth()
686 * Min of upstream link bandwidth and Endpoint CDAT bandwidth from in cxl_endpoint_gather_bandwidth()
698 * associated with the endpoint bandwidth. in cxl_endpoint_gather_bandwidth()
706 * bandwidth in cxl_endpoint_gather_bandwidth()
712 * Aggregate the computed bandwidth with the current aggregated bandwidth in cxl_endpoint_gather_bandwidth()
736 * cxl_switch_gather_bandwidth - collect all the bandwidth at switch level in an xarray in DEFINE_FREE()
746 * bandwidth, the upstream link bandwidth, and the SSLBIS of the upstream in DEFINE_FREE()
747 * switch if exists. Sum the resulting bandwidth under the switch upstream in DEFINE_FREE()
814 /* Retrieve the upstream link bandwidth */ in DEFINE_FREE()
820 * Take the min of downstream bandwidth and the upstream link in DEFINE_FREE()
821 * bandwidth. in DEFINE_FREE()
827 * switch SSLBIS bandwidth if there's a parent switch in DEFINE_FREE()
833 * Aggregate the calculated bandwidth common to an upstream in DEFINE_FREE()
843 "Asymmetric hierarchy detected, bandwidth not updated\n"); in DEFINE_FREE()
853 * cxl_rp_gather_bandwidth - handle the root port level bandwidth collection
854 * @xa: the xarray that holds the cxl_perf_ctx that has the bandwidth calculated
897 * cxl_hb_gather_bandwidth - handle the host bridge level bandwidth collection
898 * @xa: the xarray that holds the cxl_perf_ctx that has the bandwidth calculated
947 * cxl_region_update_bandwidth - Update the bandwidth access coordinates of a region
949 * @input_xa: xarray holds cxl_perf_ctx wht calculated bandwidth per ACPI0017 instance
969 * cxl_region_shared_upstream_bandwidth_update - Recalculate the bandwidth for
973 * The function walks the topology from bottom up and calculates the bandwidth. It
994 /* Collect bandwidth data from all the endpoints. */ in cxl_region_shared_upstream_bandwidth_update()
1008 "Asymmetric hierarchy detected, bandwidth not updated\n"); in cxl_region_shared_upstream_bandwidth_update()
1013 * Walk up one or more switches to deal with the bandwidth of the in cxl_region_shared_upstream_bandwidth_update()
1028 /* Handle the bandwidth at the root port of the hierarchy */ in cxl_region_shared_upstream_bandwidth_update()
1035 /* Handle the bandwidth at the host bridge of the hierarchy */ in cxl_region_shared_upstream_bandwidth_update()
1043 * Aggregate all the bandwidth collected per CFMWS (ACPI0017) and in cxl_region_shared_upstream_bandwidth_update()
1044 * update the region bandwidth with the final calculated values. in cxl_region_shared_upstream_bandwidth_update()
1061 /* Get total bandwidth and the worst latency for the cxl region */ in cxl_region_perf_data_calculate()