Lines Matching +full:cpu +full:- +full:to +full:- +full:pci

1 # SPDX-License-Identifier: GPL-2.0-only
4 	depends on PCI
11 	  CXL is a bus that is electrically compatible with PCI Express, but
13 	  CXL.mem). The CXL.cache protocol allows devices to hold cachelines
14 	  locally, the CXL.mem protocol allows devices to be fully coherent
15 	  memory targets, the CXL.io protocol is equivalent to PCI Express.
16 	  Say 'y' to enable support for the configuration and management of
22 	tristate "PCI manageability"
25 	  The CXL specification defines a "CXL memory device" sub-class in the
26 	  PCI "memory controller" base class of devices. Device's identified by
28 	  memory to be mapped into the system address map (Host-managed Device
31 	  Say 'y/m' to enable a driver that will attach to CXL memory expander
50 	  the driver it is useful to be able to submit any possible command to
51 	  the hardware, even commands that may crash the kernel due to their
52 	  potential impact to memory currently in use by the kernel.
69 	  (https://www.computeexpresslink.org/spec-landing). The CXL core
70 	  consumes these resource to publish the root of a cxl_port decode
71 	  hierarchy to map regions that represent System RAM, or Persistent
72 	  Memory regions to be managed by LIBNVDIMM.
81 	  In addition to typical memory resources a platform may also advertise
83 	  managed via a bridge driver from CXL to the LIBNVDIMM system
84 	  subsystem. Say 'y/m' to enable support for enumerating and
94 	  The CXL.mem protocol allows a device to act as a provider of "System
96 	  memory were attached to the typical CPU memory controller. This is
97 	  known as HDM "Host-managed Device Memory".
99 	  Say 'y/m' to enable a driver that will attach to CXL.mem devices for
121 	  Enable the CXL core to enumerate and provision CXL regions. A CXL
123 	  system-physical address range. For CXL regions established by
124 	  platform-firmware this option enables memory error handling to
126 	  range. Otherwise, platform-firmware managed CXL is enabled by being
136 	  the content of CPU caches without notifying those caches to
138 	  to invalidate caches when those events occur.  If that invalidation
139 	  fails the region will fail to enable.  Reasons for cache
140 	  invalidation failure are due to the CPU not providing a cache
141 	  invalidation mechanism. For example usage of wbinvd is restricted to
144 	  regions when there might be conflicting contents in the CPU cache.