3  * Support for Marvell's Cryptographic Engine and Security Accelerator (CESA)
5  * driver supports the TDMA engine on platforms on which it is available.
38 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine,  in mv_cesa_dequeue_req_locked()  argument
43 	*backlog = crypto_get_backlog(&engine->queue);  in mv_cesa_dequeue_req_locked()
44 	req = crypto_dequeue_request(&engine->queue);  in mv_cesa_dequeue_req_locked()
52 static void mv_cesa_rearm_engine(struct mv_cesa_engine *engine)  in mv_cesa_rearm_engine()  argument
58 	spin_lock_bh(&engine->lock);  in mv_cesa_rearm_engine()
59 	if (!engine->req) {  in mv_cesa_rearm_engine()
60 		req = mv_cesa_dequeue_req_locked(engine, &backlog);  in mv_cesa_rearm_engine()
61 		engine->req = req;  in mv_cesa_rearm_engine()
63 	spin_unlock_bh(&engine->lock);  in mv_cesa_rearm_engine()
75 static int mv_cesa_std_process(struct mv_cesa_engine *engine, u32 status)  in mv_cesa_std_process()  argument
81 	req = engine->req;  in mv_cesa_std_process()
87 		mv_cesa_engine_enqueue_complete_request(engine, req);  in mv_cesa_std_process()
95 static int mv_cesa_int_process(struct mv_cesa_engine *engine, u32 status)  in mv_cesa_int_process()  argument
97 	if (engine->chain.first && engine->chain.last)  in mv_cesa_int_process()
98 		return mv_cesa_tdma_process(engine, status);  in mv_cesa_int_process()
100 	return mv_cesa_std_process(engine, status);  in mv_cesa_int_process()
115 	struct mv_cesa_engine *engine = priv;  in mv_cesa_int()  local
124 		mask = mv_cesa_get_int_mask(engine);  in mv_cesa_int()
125 		status = readl(engine->regs + CESA_SA_INT_STATUS);  in mv_cesa_int()
134 		writel(~status, engine->regs + CESA_SA_FPGA_INT_STATUS);  in mv_cesa_int()
135 		writel(~status, engine->regs + CESA_SA_INT_STATUS);  in mv_cesa_int()
138 		res = mv_cesa_int_process(engine, status & mask);  in mv_cesa_int()
141 		spin_lock_bh(&engine->lock);  in mv_cesa_int()
142 		req = engine->req;  in mv_cesa_int()
144 			engine->req = NULL;  in mv_cesa_int()
145 		spin_unlock_bh(&engine->lock);  in mv_cesa_int()
153 		mv_cesa_rearm_engine(engine);  in mv_cesa_int()
157 			req = mv_cesa_engine_dequeue_complete_request(engine);  in mv_cesa_int()
173 	struct mv_cesa_engine *engine = creq->engine;  in mv_cesa_queue_req()  local
175 	spin_lock_bh(&engine->lock);  in mv_cesa_queue_req()
176 	ret = crypto_enqueue_request(&engine->queue, req);  in mv_cesa_queue_req()
179 		mv_cesa_tdma_chain(engine, creq);  in mv_cesa_queue_req()
180 	spin_unlock_bh(&engine->lock);  in mv_cesa_queue_req()
185 	mv_cesa_rearm_engine(engine);  in mv_cesa_queue_req()
315 mv_cesa_conf_mbus_windows(struct mv_cesa_engine *engine,  in mv_cesa_conf_mbus_windows()  argument
318 	void __iomem *iobase = engine->regs;  in mv_cesa_conf_mbus_windows()
377 	struct mv_cesa_engine *engine = &cesa->engines[idx];  in mv_cesa_get_sram()  local
380 	engine->pool = of_gen_pool_get(cesa->dev->of_node,  in mv_cesa_get_sram()
382 	if (engine->pool) {  in mv_cesa_get_sram()
383 		engine->sram_pool = gen_pool_dma_alloc(engine->pool,  in mv_cesa_get_sram()
385 						       &engine->sram_dma);  in mv_cesa_get_sram()
386 		if (engine->sram_pool)  in mv_cesa_get_sram()
389 		engine->pool = NULL;  in mv_cesa_get_sram()
393 	engine->sram = devm_platform_get_and_ioremap_resource(pdev, idx, &res);  in mv_cesa_get_sram()
394 	if (IS_ERR(engine->sram))  in mv_cesa_get_sram()
395 		return PTR_ERR(engine->sram);  in mv_cesa_get_sram()
397 	engine->sram_dma = dma_map_resource(cesa->dev, res->start,  in mv_cesa_get_sram()
400 	if (dma_mapping_error(cesa->dev, engine->sram_dma))  in mv_cesa_get_sram()
409 	struct mv_cesa_engine *engine = &cesa->engines[idx];  in mv_cesa_put_sram()  local
411 	if (engine->pool)  in mv_cesa_put_sram()
412 		gen_pool_free(engine->pool, (unsigned long)engine->sram_pool,  in mv_cesa_put_sram()
415 		dma_unmap_resource(cesa->dev, engine->sram_dma,  in mv_cesa_put_sram()
477 		struct mv_cesa_engine *engine = &cesa->engines[i];  in mv_cesa_probe()  local
480 		engine->id = i;  in mv_cesa_probe()
481 		spin_lock_init(&engine->lock);  in mv_cesa_probe()
493 		engine->irq = irq;  in mv_cesa_probe()
500 		engine->clk = devm_clk_get_optional_enabled(dev, res_name);  in mv_cesa_probe()
501 		if (IS_ERR(engine->clk)) {  in mv_cesa_probe()
502 			engine->clk = devm_clk_get_optional_enabled(dev, NULL);  in mv_cesa_probe()
503 			if (IS_ERR(engine->clk)) {  in mv_cesa_probe()
504 				ret = PTR_ERR(engine->clk);  in mv_cesa_probe()
510 		engine->zclk = devm_clk_get_optional_enabled(dev, res_name);  in mv_cesa_probe()
511 		if (IS_ERR(engine->zclk)) {  in mv_cesa_probe()
512 			ret = PTR_ERR(engine->zclk);  in mv_cesa_probe()
516 		engine->regs = cesa->regs + CESA_ENGINE_OFF(i);  in mv_cesa_probe()
519 			mv_cesa_conf_mbus_windows(engine, dram);  in mv_cesa_probe()
521 		writel(0, engine->regs + CESA_SA_INT_STATUS);  in mv_cesa_probe()
523 		       engine->regs + CESA_SA_CFG);  in mv_cesa_probe()
524 		writel(engine->sram_dma & CESA_SA_SRAM_MSK,  in mv_cesa_probe()
525 		       engine->regs + CESA_SA_DESC_P0);  in mv_cesa_probe()
530 						engine);  in mv_cesa_probe()
535 		cpu = cpumask_local_spread(engine->id, NUMA_NO_NODE);  in mv_cesa_probe()
538 		crypto_init_queue(&engine->queue, CESA_CRYPTO_DEFAULT_MAX_QLEN);  in mv_cesa_probe()
539 		atomic_set(&engine->load, 0);  in mv_cesa_probe()
540 		INIT_LIST_HEAD(&engine->complete_queue);  in mv_cesa_probe()
592 MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");