Lines Matching +full:dfx +full:- +full:bus
1 // SPDX-License-Identifier: GPL-2.0
313 /* define the ZIP's dfx regs region and region length */
347 struct hisi_qm *qm = s->private; in hzip_diff_regs_show()
349 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in hzip_diff_regs_show()
362 return -EINVAL; in perf_mode_set()
367 return -EINVAL; in perf_mode_set()
414 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)");
423 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
444 cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_TB].cap_val; in hisi_zip_alg_support()
456 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
463 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
464 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, in hisi_zip_set_high_perf()
468 pci_err(qm->pdev, "failed to set perf mode\n"); in hisi_zip_set_high_perf()
478 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) in hisi_zip_open_sva_prefetch()
482 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
484 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
486 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, in hisi_zip_open_sva_prefetch()
490 pci_err(qm->pdev, "failed to open sva prefetch\n"); in hisi_zip_open_sva_prefetch()
498 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) in hisi_zip_close_sva_prefetch()
501 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
503 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
505 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, in hisi_zip_close_sva_prefetch()
509 pci_err(qm->pdev, "failed to close sva prefetch\n"); in hisi_zip_close_sva_prefetch()
516 if (qm->ver < QM_HW_V3) in hisi_zip_enable_clock_gate()
519 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); in hisi_zip_enable_clock_gate()
521 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); in hisi_zip_enable_clock_gate()
523 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE); in hisi_zip_enable_clock_gate()
525 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE); in hisi_zip_enable_clock_gate()
530 void __iomem *base = qm->io_base; in hisi_zip_set_user_domain_and_cache()
545 /* disable FLR triggered by BME(bus master enable) */ in hisi_zip_set_user_domain_and_cache()
559 if (qm->use_sva && qm->ver == QM_HW_V2) { in hisi_zip_set_user_domain_and_cache()
571 zip_core_en = qm->cap_tables.dev_cap_table[ZIP_CORE_EN].cap_val; in hisi_zip_set_user_domain_and_cache()
592 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_master_ooo_ctrl()
596 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in hisi_zip_master_ooo_ctrl()
602 if (qm->ver > QM_HW_V2) in hisi_zip_master_ooo_ctrl()
603 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); in hisi_zip_master_ooo_ctrl()
605 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_master_ooo_ctrl()
612 if (qm->ver == QM_HW_V1) { in hisi_zip_hw_error_enable()
614 qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
615 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); in hisi_zip_hw_error_enable()
619 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); in hisi_zip_hw_error_enable()
620 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); in hisi_zip_hw_error_enable()
623 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE); in hisi_zip_hw_error_enable()
626 writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); in hisi_zip_hw_error_enable()
627 writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); in hisi_zip_hw_error_enable()
628 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_hw_error_enable()
633 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
643 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); in hisi_zip_hw_error_disable()
644 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); in hisi_zip_hw_error_disable()
645 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_disable()
654 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; in file_to_qm()
656 return &hisi_zip->qm; in file_to_qm()
661 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & in clear_enable_read()
670 return -EINVAL; in clear_enable_write()
672 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & in clear_enable_write()
674 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); in clear_enable_write()
682 struct ctrl_debug_file *file = filp->private_data; in hisi_zip_ctrl_debug_read()
692 spin_lock_irq(&file->lock); in hisi_zip_ctrl_debug_read()
693 switch (file->index) { in hisi_zip_ctrl_debug_read()
700 spin_unlock_irq(&file->lock); in hisi_zip_ctrl_debug_read()
707 spin_unlock_irq(&file->lock); in hisi_zip_ctrl_debug_read()
709 return -EINVAL; in hisi_zip_ctrl_debug_read()
716 struct ctrl_debug_file *file = filp->private_data; in hisi_zip_ctrl_debug_write()
726 return -ENOSPC; in hisi_zip_ctrl_debug_write()
728 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); in hisi_zip_ctrl_debug_write()
741 spin_lock_irq(&file->lock); in hisi_zip_ctrl_debug_write()
742 switch (file->index) { in hisi_zip_ctrl_debug_write()
749 ret = -EINVAL; in hisi_zip_ctrl_debug_write()
756 spin_unlock_irq(&file->lock); in hisi_zip_ctrl_debug_write()
771 return -EINVAL; in zip_debugfs_atomic64_set()
790 hisi_qm_regs_dump(s, s->private); in hisi_zip_regs_show()
802 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; in get_zip_core_addr()
807 return qm->io_base + HZIP_CORE_DFX_BASE + in get_zip_core_addr()
810 return qm->io_base + HZIP_CORE_DFX_DECOMP_BASE + in get_zip_core_addr()
811 (core_num - zip_comp_core_num) * HZIP_CORE_ADDR_INTRVL; in get_zip_core_addr()
817 struct device *dev = &qm->pdev->dev; in hisi_zip_core_debug_init()
824 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; in hisi_zip_core_debug_init()
835 i - zip_comp_core_num); in hisi_zip_core_debug_init()
839 return -ENOENT; in hisi_zip_core_debug_init()
841 regset->regs = hzip_dfx_regs; in hisi_zip_core_debug_init()
842 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); in hisi_zip_core_debug_init()
843 regset->base = get_zip_core_addr(qm, i); in hisi_zip_core_debug_init()
844 regset->dev = dev; in hisi_zip_core_debug_init()
846 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); in hisi_zip_core_debug_init()
856 struct hisi_qm *qm = s->private; in zip_cap_regs_show()
859 size = qm->cap_tables.qm_cap_size; in zip_cap_regs_show()
861 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name, in zip_cap_regs_show()
862 qm->cap_tables.qm_cap_table[i].cap_val); in zip_cap_regs_show()
864 size = qm->cap_tables.dev_cap_size; in zip_cap_regs_show()
866 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name, in zip_cap_regs_show()
867 qm->cap_tables.dev_cap_table[i].cap_val); in zip_cap_regs_show()
876 struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs; in hisi_zip_dfx_debug_init()
878 struct hisi_zip_dfx *dfx = &zip->dfx; in hisi_zip_dfx_debug_init() local
883 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); in hisi_zip_dfx_debug_init()
885 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); in hisi_zip_dfx_debug_init()
891 if (qm->fun_type == QM_HW_PF && hzip_regs) in hisi_zip_dfx_debug_init()
896 qm->debug.debug_root, qm, &zip_cap_regs_fops); in hisi_zip_dfx_debug_init()
905 spin_lock_init(&zip->ctrl->files[i].lock); in hisi_zip_ctrl_debug_init()
906 zip->ctrl->files[i].ctrl = zip->ctrl; in hisi_zip_ctrl_debug_init()
907 zip->ctrl->files[i].index = i; in hisi_zip_ctrl_debug_init()
910 qm->debug.debug_root, in hisi_zip_ctrl_debug_init()
911 zip->ctrl->files + i, in hisi_zip_ctrl_debug_init()
920 struct device *dev = &qm->pdev->dev; in hisi_zip_debugfs_init()
929 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; in hisi_zip_debugfs_init()
930 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; in hisi_zip_debugfs_init()
931 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), in hisi_zip_debugfs_init()
936 if (qm->fun_type == QM_HW_PF) { in hisi_zip_debugfs_init()
947 debugfs_remove_recursive(qm->debug.debug_root); in hisi_zip_debugfs_init()
952 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */
959 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; in hisi_zip_debug_regs_clear()
964 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); in hisi_zip_debug_regs_clear()
971 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); in hisi_zip_debug_regs_clear()
978 debugfs_remove_recursive(qm->debug.debug_root); in hisi_zip_debugfs_exit()
982 if (qm->fun_type == QM_HW_PF) { in hisi_zip_debugfs_exit()
984 qm->debug.curr_qm_qp_num = 0; in hisi_zip_debugfs_exit()
992 struct qm_debug *debug = &qm->debug; in hisi_zip_show_last_regs_init()
998 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; in hisi_zip_show_last_regs_init()
1002 debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num, in hisi_zip_show_last_regs_init()
1004 if (!debug->last_words) in hisi_zip_show_last_regs_init()
1005 return -ENOMEM; in hisi_zip_show_last_regs_init()
1008 io_base = qm->io_base + hzip_com_dfx_regs[i].offset; in hisi_zip_show_last_regs_init()
1009 debug->last_words[i] = readl_relaxed(io_base); in hisi_zip_show_last_regs_init()
1016 debug->last_words[idx] = readl_relaxed( in hisi_zip_show_last_regs_init()
1026 struct qm_debug *debug = &qm->debug; in hisi_zip_show_last_regs_uninit()
1028 if (qm->fun_type == QM_HW_VF || !debug->last_words) in hisi_zip_show_last_regs_uninit()
1031 kfree(debug->last_words); in hisi_zip_show_last_regs_uninit()
1032 debug->last_words = NULL; in hisi_zip_show_last_regs_uninit()
1040 struct qm_debug *debug = &qm->debug; in hisi_zip_show_last_dfx_regs()
1047 if (qm->fun_type == QM_HW_VF || !debug->last_words) in hisi_zip_show_last_dfx_regs()
1051 val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset); in hisi_zip_show_last_dfx_regs()
1052 if (debug->last_words[i] != val) in hisi_zip_show_last_dfx_regs()
1053 pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n", in hisi_zip_show_last_dfx_regs()
1054 hzip_com_dfx_regs[i].name, debug->last_words[i], val); in hisi_zip_show_last_dfx_regs()
1057 zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val; in hisi_zip_show_last_dfx_regs()
1065 scnprintf(buf, sizeof(buf), "Comp_core-%d", i); in hisi_zip_show_last_dfx_regs()
1067 scnprintf(buf, sizeof(buf), "Decomp_core-%d", in hisi_zip_show_last_dfx_regs()
1068 i - zip_comp_core_num); in hisi_zip_show_last_dfx_regs()
1071 pci_info(qm->pdev, "==>%s:\n", buf); in hisi_zip_show_last_dfx_regs()
1072 /* dump last word for dfx regs during control resetting */ in hisi_zip_show_last_dfx_regs()
1076 if (debug->last_words[idx] != val) in hisi_zip_show_last_dfx_regs()
1077 pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n", in hisi_zip_show_last_dfx_regs()
1079 debug->last_words[idx], val); in hisi_zip_show_last_dfx_regs()
1087 struct device *dev = &qm->pdev->dev; in hisi_zip_log_hw_error()
1090 while (err->msg) { in hisi_zip_log_hw_error()
1091 if (err->int_msk & err_sts) { in hisi_zip_log_hw_error()
1093 err->msg, err->int_msk); in hisi_zip_log_hw_error()
1095 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { in hisi_zip_log_hw_error()
1096 err_val = readl(qm->io_base + in hisi_zip_log_hw_error()
1098 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", in hisi_zip_log_hw_error()
1109 return readl(qm->io_base + HZIP_CORE_INT_STATUS); in hisi_zip_get_hw_err_status()
1114 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); in hisi_zip_clear_hw_err_status()
1121 nfe_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); in hisi_zip_disable_error_report()
1122 writel(nfe_mask & (~err_type), qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_disable_error_report()
1129 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_open_axi_master_ooo()
1132 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_open_axi_master_ooo()
1135 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_open_axi_master_ooo()
1145 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_close_axi_master_ooo()
1147 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_close_axi_master_ooo()
1151 qm->io_base + HZIP_CORE_INT_SET); in hisi_zip_close_axi_master_ooo()
1163 if (err_status & qm->err_info.ecc_2bits_mask) in hisi_zip_get_err_result()
1164 qm->err_status.is_dev_ecc_mbit = true; in hisi_zip_get_err_result()
1167 if (err_status & qm->err_info.dev_reset_mask) { in hisi_zip_get_err_result()
1188 if (err_status & qm->err_info.dev_shutdown_mask) in hisi_zip_dev_is_abnormal()
1201 struct hisi_qm_err_info *err_info = &qm->err_info; in hisi_zip_err_info_init()
1203 err_info->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; in hisi_zip_err_info_init()
1204 err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
1205 err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
1206 ZIP_QM_NFE_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
1207 err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; in hisi_zip_err_info_init()
1208 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
1209 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
1210 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
1211 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
1212 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
1213 ZIP_QM_RESET_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
1214 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
1215 ZIP_RESET_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
1216 err_info->msi_wr_port = HZIP_WR_PORT; in hisi_zip_err_info_init()
1217 err_info->acpi_rst = "ZRST"; in hisi_zip_err_info_init()
1239 struct hisi_qm *qm = &hisi_zip->qm; in hisi_zip_pf_probe_init()
1243 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); in hisi_zip_pf_probe_init()
1245 return -ENOMEM; in hisi_zip_pf_probe_init()
1247 hisi_zip->ctrl = ctrl; in hisi_zip_pf_probe_init()
1248 ctrl->hisi_zip = hisi_zip; in hisi_zip_pf_probe_init()
1264 pci_err(qm->pdev, "Failed to init last word regs!\n"); in hisi_zip_pf_probe_init()
1272 struct pci_dev *pdev = qm->pdev; in zip_pre_store_cap_reg()
1276 zip_cap = devm_kzalloc(&pdev->dev, sizeof(*zip_cap) * size, GFP_KERNEL); in zip_pre_store_cap_reg()
1278 return -ENOMEM; in zip_pre_store_cap_reg()
1284 i, qm->cap_ver); in zip_pre_store_cap_reg()
1287 qm->cap_tables.dev_cap_table = zip_cap; in zip_pre_store_cap_reg()
1288 qm->cap_tables.dev_cap_size = size; in zip_pre_store_cap_reg()
1298 qm->pdev = pdev; in hisi_zip_qm_init()
1299 qm->mode = uacce_mode; in hisi_zip_qm_init()
1300 qm->sqe_size = HZIP_SQE_SIZE; in hisi_zip_qm_init()
1301 qm->dev_name = hisi_zip_name; in hisi_zip_qm_init()
1303 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ? in hisi_zip_qm_init()
1305 if (qm->fun_type == QM_HW_PF) { in hisi_zip_qm_init()
1306 qm->qp_base = HZIP_PF_DEF_Q_BASE; in hisi_zip_qm_init()
1307 qm->qp_num = pf_q_num; in hisi_zip_qm_init()
1308 qm->debug.curr_qm_qp_num = pf_q_num; in hisi_zip_qm_init()
1309 qm->qm_list = &zip_devices; in hisi_zip_qm_init()
1310 qm->err_ini = &hisi_zip_err_ini; in hisi_zip_qm_init()
1312 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); in hisi_zip_qm_init()
1313 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { in hisi_zip_qm_init()
1321 qm->qp_base = HZIP_PF_DEF_Q_NUM; in hisi_zip_qm_init()
1322 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; in hisi_zip_qm_init()
1327 pci_err(qm->pdev, "Failed to init zip qm configures!\n"); in hisi_zip_qm_init()
1334 pci_err(qm->pdev, "Failed to pre-store capability registers!\n"); in hisi_zip_qm_init()
1338 alg_msk = qm->cap_tables.dev_cap_table[ZIP_ALG_BITMAP].cap_val; in hisi_zip_qm_init()
1341 pci_err(qm->pdev, "Failed to set zip algs!\n"); in hisi_zip_qm_init()
1364 struct hisi_qm *qm = &hisi_zip->qm; in hisi_zip_probe_init()
1367 if (qm->fun_type == QM_HW_PF) { in hisi_zip_probe_init()
1372 if (qm->ver >= QM_HW_V3) { in hisi_zip_probe_init()
1377 qm->type_rate = type_rate; in hisi_zip_probe_init()
1386 if (qm->fun_type == QM_HW_VF) in hisi_zip_probe_uninit()
1400 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); in hisi_zip_probe()
1402 return -ENOMEM; in hisi_zip_probe()
1404 qm = &hisi_zip->qm; in hisi_zip_probe()
1433 if (qm->uacce) { in hisi_zip_probe()
1434 ret = uacce_register(qm->uacce); in hisi_zip_probe()
1441 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { in hisi_zip_probe()
1477 if (qm->fun_type == QM_HW_PF && qm->vfs_num) in hisi_zip_remove()