347 	struct hisi_qm *qm = s->private;  in hzip_diff_regs_show()  local
349 	hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,  in hzip_diff_regs_show()
440 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg)  in hisi_zip_alg_support()  argument
444 	cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_TB].cap_val;  in hisi_zip_alg_support()
451 static int hisi_zip_set_high_perf(struct hisi_qm *qm)  in hisi_zip_set_high_perf()  argument
456 	val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET);  in hisi_zip_set_high_perf()
463 	writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET);  in hisi_zip_set_high_perf()
464 	ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET,  in hisi_zip_set_high_perf()
468 		pci_err(qm->pdev, "failed to set perf mode\n");  in hisi_zip_set_high_perf()
473 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm)  in hisi_zip_open_sva_prefetch()  argument
478 	if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))  in hisi_zip_open_sva_prefetch()
482 	val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG);  in hisi_zip_open_sva_prefetch()
484 	writel(val, qm->io_base + HZIP_PREFETCH_CFG);  in hisi_zip_open_sva_prefetch()
486 	ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG,  in hisi_zip_open_sva_prefetch()
490 		pci_err(qm->pdev, "failed to open sva prefetch\n");  in hisi_zip_open_sva_prefetch()
493 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm)  in hisi_zip_close_sva_prefetch()  argument
498 	if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))  in hisi_zip_close_sva_prefetch()
501 	val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG);  in hisi_zip_close_sva_prefetch()
503 	writel(val, qm->io_base + HZIP_PREFETCH_CFG);  in hisi_zip_close_sva_prefetch()
505 	ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS,  in hisi_zip_close_sva_prefetch()
509 		pci_err(qm->pdev, "failed to close sva prefetch\n");  in hisi_zip_close_sva_prefetch()
512 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm)  in hisi_zip_enable_clock_gate()  argument
516 	if (qm->ver < QM_HW_V3)  in hisi_zip_enable_clock_gate()
519 	val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL);  in hisi_zip_enable_clock_gate()
521 	writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL);  in hisi_zip_enable_clock_gate()
523 	val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE);  in hisi_zip_enable_clock_gate()
525 	writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE);  in hisi_zip_enable_clock_gate()
528 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm)  in hisi_zip_set_user_domain_and_cache()  argument
530 	void __iomem *base = qm->io_base;  in hisi_zip_set_user_domain_and_cache()
534 	/* qm user domain */  in hisi_zip_set_user_domain_and_cache()
541 	/* qm cache */  in hisi_zip_set_user_domain_and_cache()
559 	if (qm->use_sva && qm->ver == QM_HW_V2) {  in hisi_zip_set_user_domain_and_cache()
571 	zip_core_en = qm->cap_tables.dev_cap_table[ZIP_CORE_EN].cap_val;  in hisi_zip_set_user_domain_and_cache()
583 	hisi_zip_enable_clock_gate(qm);  in hisi_zip_set_user_domain_and_cache()
585 	return hisi_dae_set_user_domain(qm);  in hisi_zip_set_user_domain_and_cache()
588 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable)  in hisi_zip_master_ooo_ctrl()  argument
592 	val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);  in hisi_zip_master_ooo_ctrl()
595 		val2 = hisi_qm_get_hw_info(qm, zip_basic_cap_info,  in hisi_zip_master_ooo_ctrl()
596 				ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);  in hisi_zip_master_ooo_ctrl()
602 	if (qm->ver > QM_HW_V2)  in hisi_zip_master_ooo_ctrl()
603 		writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL);  in hisi_zip_master_ooo_ctrl()
605 	writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);  in hisi_zip_master_ooo_ctrl()
608 static void hisi_zip_hw_error_enable(struct hisi_qm *qm)  in hisi_zip_hw_error_enable()  argument
612 	if (qm->ver == QM_HW_V1) {  in hisi_zip_hw_error_enable()
614 		       qm->io_base + HZIP_CORE_INT_MASK_REG);  in hisi_zip_hw_error_enable()
615 		dev_info(&qm->pdev->dev, "Does not support hw error handle\n");  in hisi_zip_hw_error_enable()
619 	nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver);  in hisi_zip_hw_error_enable()
620 	ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver);  in hisi_zip_hw_error_enable()
623 	writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE);  in hisi_zip_hw_error_enable()
626 	writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);  in hisi_zip_hw_error_enable()
627 	writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);  in hisi_zip_hw_error_enable()
628 	writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);  in hisi_zip_hw_error_enable()
630 	hisi_zip_master_ooo_ctrl(qm, true);  in hisi_zip_hw_error_enable()
633 	writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG);  in hisi_zip_hw_error_enable()
635 	hisi_dae_hw_error_enable(qm);  in hisi_zip_hw_error_enable()
638 static void hisi_zip_hw_error_disable(struct hisi_qm *qm)  in hisi_zip_hw_error_disable()  argument
643 	nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver);  in hisi_zip_hw_error_disable()
644 	ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver);  in hisi_zip_hw_error_disable()
645 	writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG);  in hisi_zip_hw_error_disable()
647 	hisi_zip_master_ooo_ctrl(qm, false);  in hisi_zip_hw_error_disable()
649 	hisi_dae_hw_error_disable(qm);  in hisi_zip_hw_error_disable()
656 	return &hisi_zip->qm;  in file_to_qm()
659 static u32 clear_enable_read(struct hisi_qm *qm)  in clear_enable_read()  argument
661 	return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &  in clear_enable_read()
665 static int clear_enable_write(struct hisi_qm *qm, u32 val)  in clear_enable_write()  argument
672 	tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &  in clear_enable_write()
674 	writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);  in clear_enable_write()
683 	struct hisi_qm *qm = file_to_qm(file);  in hisi_zip_ctrl_debug_read()  local
688 	ret = hisi_qm_get_dfx_access(qm);  in hisi_zip_ctrl_debug_read()
695 		val = clear_enable_read(qm);  in hisi_zip_ctrl_debug_read()
702 	hisi_qm_put_dfx_access(qm);  in hisi_zip_ctrl_debug_read()
708 	hisi_qm_put_dfx_access(qm);  in hisi_zip_ctrl_debug_read()
717 	struct hisi_qm *qm = file_to_qm(file);  in hisi_zip_ctrl_debug_write()  local
737 	ret = hisi_qm_get_dfx_access(qm);  in hisi_zip_ctrl_debug_write()
744 		ret = clear_enable_write(qm, val);  in hisi_zip_ctrl_debug_write()
757 	hisi_qm_put_dfx_access(qm);  in hisi_zip_ctrl_debug_write()
797 static void __iomem *get_zip_core_addr(struct hisi_qm *qm, int core_num)  in get_zip_core_addr()  argument
802 	zip_core_info =  qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;  in get_zip_core_addr()
807 		return qm->io_base + HZIP_CORE_DFX_BASE +  in get_zip_core_addr()
810 	return qm->io_base + HZIP_CORE_DFX_DECOMP_BASE +  in get_zip_core_addr()
814 static int hisi_zip_core_debug_init(struct hisi_qm *qm)  in hisi_zip_core_debug_init()  argument
817 	struct device *dev = &qm->pdev->dev;  in hisi_zip_core_debug_init()
824 	zip_core_info =  qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;  in hisi_zip_core_debug_init()
843 		regset->base = get_zip_core_addr(qm, i);  in hisi_zip_core_debug_init()
846 		tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);  in hisi_zip_core_debug_init()
856 	struct hisi_qm *qm = s->private;  in zip_cap_regs_show()  local
859 	size = qm->cap_tables.qm_cap_size;  in zip_cap_regs_show()
861 		seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name,  in zip_cap_regs_show()
862 			   qm->cap_tables.qm_cap_table[i].cap_val);  in zip_cap_regs_show()
864 	size = qm->cap_tables.dev_cap_size;  in zip_cap_regs_show()
866 		seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name,  in zip_cap_regs_show()
867 			   qm->cap_tables.dev_cap_table[i].cap_val);  in zip_cap_regs_show()
874 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm)  in hisi_zip_dfx_debug_init()  argument
876 	struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs;  in hisi_zip_dfx_debug_init()
877 	struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);  in hisi_zip_dfx_debug_init()
883 	tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root);  in hisi_zip_dfx_debug_init()
891 	if (qm->fun_type == QM_HW_PF && hzip_regs)  in hisi_zip_dfx_debug_init()
893 				      qm, &hzip_diff_regs_fops);  in hisi_zip_dfx_debug_init()
896 			    qm->debug.debug_root, qm, &zip_cap_regs_fops);  in hisi_zip_dfx_debug_init()
899 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm)  in hisi_zip_ctrl_debug_init()  argument
901 	struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);  in hisi_zip_ctrl_debug_init()
910 				    qm->debug.debug_root,  in hisi_zip_ctrl_debug_init()
915 	return hisi_zip_core_debug_init(qm);  in hisi_zip_ctrl_debug_init()
918 static int hisi_zip_debugfs_init(struct hisi_qm *qm)  in hisi_zip_debugfs_init()  argument
920 	struct device *dev = &qm->pdev->dev;  in hisi_zip_debugfs_init()
923 	ret = hisi_qm_regs_debugfs_init(qm, hzip_diff_regs, ARRAY_SIZE(hzip_diff_regs));  in hisi_zip_debugfs_init()
929 	qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET;  in hisi_zip_debugfs_init()
930 	qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN;  in hisi_zip_debugfs_init()
931 	qm->debug.debug_root = debugfs_create_dir(dev_name(dev),  in hisi_zip_debugfs_init()
934 	hisi_qm_debug_init(qm);  in hisi_zip_debugfs_init()
936 	if (qm->fun_type == QM_HW_PF) {  in hisi_zip_debugfs_init()
937 		ret = hisi_zip_ctrl_debug_init(qm);  in hisi_zip_debugfs_init()
942 	hisi_zip_dfx_debug_init(qm);  in hisi_zip_debugfs_init()
947 	debugfs_remove_recursive(qm->debug.debug_root);  in hisi_zip_debugfs_init()
948 	hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs));  in hisi_zip_debugfs_init()
953 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm)  in hisi_zip_debug_regs_clear()  argument
959 	zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;  in hisi_zip_debug_regs_clear()
964 	writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);  in hisi_zip_debug_regs_clear()
967 			readl(get_zip_core_addr(qm, i) +  in hisi_zip_debug_regs_clear()
971 	writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);  in hisi_zip_debug_regs_clear()
973 	hisi_qm_debug_regs_clear(qm);  in hisi_zip_debug_regs_clear()
976 static void hisi_zip_debugfs_exit(struct hisi_qm *qm)  in hisi_zip_debugfs_exit()  argument
978 	debugfs_remove_recursive(qm->debug.debug_root);  in hisi_zip_debugfs_exit()
980 	hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs));  in hisi_zip_debugfs_exit()
982 	if (qm->fun_type == QM_HW_PF) {  in hisi_zip_debugfs_exit()
983 		hisi_zip_debug_regs_clear(qm);  in hisi_zip_debugfs_exit()
984 		qm->debug.curr_qm_qp_num = 0;  in hisi_zip_debugfs_exit()
988 static int hisi_zip_show_last_regs_init(struct hisi_qm *qm)  in hisi_zip_show_last_regs_init()  argument
992 	struct qm_debug *debug = &qm->debug;  in hisi_zip_show_last_regs_init()
998 	zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;  in hisi_zip_show_last_regs_init()
1008 		io_base = qm->io_base + hzip_com_dfx_regs[i].offset;  in hisi_zip_show_last_regs_init()
1013 		io_base = get_zip_core_addr(qm, i);  in hisi_zip_show_last_regs_init()
1024 static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm)  in hisi_zip_show_last_regs_uninit()  argument
1026 	struct qm_debug *debug = &qm->debug;  in hisi_zip_show_last_regs_uninit()
1028 	if (qm->fun_type == QM_HW_VF || !debug->last_words)  in hisi_zip_show_last_regs_uninit()
1035 static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm)  in hisi_zip_show_last_dfx_regs()  argument
1040 	struct qm_debug *debug = &qm->debug;  in hisi_zip_show_last_dfx_regs()
1047 	if (qm->fun_type == QM_HW_VF || !debug->last_words)  in hisi_zip_show_last_dfx_regs()
1051 		val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset);  in hisi_zip_show_last_dfx_regs()
1053 			pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n",  in hisi_zip_show_last_dfx_regs()
1057 	zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;  in hisi_zip_show_last_dfx_regs()
1069 		base = get_zip_core_addr(qm, i);  in hisi_zip_show_last_dfx_regs()
1071 		pci_info(qm->pdev, "==>%s:\n", buf);  in hisi_zip_show_last_dfx_regs()
1077 				pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n",  in hisi_zip_show_last_dfx_regs()
1084 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts)  in hisi_zip_log_hw_error()  argument
1087 	struct device *dev = &qm->pdev->dev;  in hisi_zip_log_hw_error()
1096 				err_val = readl(qm->io_base +  in hisi_zip_log_hw_error()
1107 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm)  in hisi_zip_get_hw_err_status()  argument
1109 	return readl(qm->io_base + HZIP_CORE_INT_STATUS);  in hisi_zip_get_hw_err_status()
1112 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)  in hisi_zip_clear_hw_err_status()  argument
1114 	writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);  in hisi_zip_clear_hw_err_status()
1117 static void hisi_zip_disable_error_report(struct hisi_qm *qm, u32 err_type)  in hisi_zip_disable_error_report()  argument
1121 	nfe_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver);  in hisi_zip_disable_error_report()
1122 	writel(nfe_mask & (~err_type), qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);  in hisi_zip_disable_error_report()
1125 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm)  in hisi_zip_open_axi_master_ooo()  argument
1129 	val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);  in hisi_zip_open_axi_master_ooo()
1132 	       qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);  in hisi_zip_open_axi_master_ooo()
1135 	       qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);  in hisi_zip_open_axi_master_ooo()
1137 	hisi_dae_open_axi_master_ooo(qm);  in hisi_zip_open_axi_master_ooo()
1140 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm)  in hisi_zip_close_axi_master_ooo()  argument
1145 	nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);  in hisi_zip_close_axi_master_ooo()
1147 	       qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);  in hisi_zip_close_axi_master_ooo()
1151 	       qm->io_base + HZIP_CORE_INT_SET);  in hisi_zip_close_axi_master_ooo()
1154 static enum acc_err_result hisi_zip_get_err_result(struct hisi_qm *qm)  in hisi_zip_get_err_result()  argument
1161 	err_status = hisi_zip_get_hw_err_status(qm);  in hisi_zip_get_err_result()
1163 		if (err_status & qm->err_info.ecc_2bits_mask)  in hisi_zip_get_err_result()
1164 			qm->err_status.is_dev_ecc_mbit = true;  in hisi_zip_get_err_result()
1165 		hisi_zip_log_hw_error(qm, err_status);  in hisi_zip_get_err_result()
1167 		if (err_status & qm->err_info.dev_reset_mask) {  in hisi_zip_get_err_result()
1169 			hisi_zip_disable_error_report(qm, err_status);  in hisi_zip_get_err_result()
1172 			hisi_zip_clear_hw_err_status(qm, err_status);  in hisi_zip_get_err_result()
1176 	dae_result = hisi_dae_get_err_result(qm);  in hisi_zip_get_err_result()
1183 static bool hisi_zip_dev_is_abnormal(struct hisi_qm *qm)  in hisi_zip_dev_is_abnormal()  argument
1187 	err_status = hisi_zip_get_hw_err_status(qm);  in hisi_zip_dev_is_abnormal()
1188 	if (err_status & qm->err_info.dev_shutdown_mask)  in hisi_zip_dev_is_abnormal()
1191 	return hisi_dae_dev_is_abnormal(qm);  in hisi_zip_dev_is_abnormal()
1194 static int hisi_zip_set_priv_status(struct hisi_qm *qm)  in hisi_zip_set_priv_status()  argument
1196 	return hisi_dae_close_axi_master_ooo(qm);  in hisi_zip_set_priv_status()
1199 static void hisi_zip_err_info_init(struct hisi_qm *qm)  in hisi_zip_err_info_init()  argument
1201 	struct hisi_qm_err_info *err_info = &qm->err_info;  in hisi_zip_err_info_init()
1204 	err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver);  in hisi_zip_err_info_init()
1205 	err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info,  in hisi_zip_err_info_init()
1206 					    ZIP_QM_NFE_MASK_CAP, qm->cap_ver);  in hisi_zip_err_info_init()
1208 	err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,  in hisi_zip_err_info_init()
1209 							 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);  in hisi_zip_err_info_init()
1210 	err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,  in hisi_zip_err_info_init()
1211 							  ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);  in hisi_zip_err_info_init()
1212 	err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,  in hisi_zip_err_info_init()
1213 						      ZIP_QM_RESET_MASK_CAP, qm->cap_ver);  in hisi_zip_err_info_init()
1214 	err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,  in hisi_zip_err_info_init()
1215 						       ZIP_RESET_MASK_CAP, qm->cap_ver);  in hisi_zip_err_info_init()
1239 	struct hisi_qm *qm = &hisi_zip->qm;  in hisi_zip_pf_probe_init()  local
1243 	ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL);  in hisi_zip_pf_probe_init()
1250 	ret = hisi_zip_set_user_domain_and_cache(qm);  in hisi_zip_pf_probe_init()
1254 	ret = hisi_zip_set_high_perf(qm);  in hisi_zip_pf_probe_init()
1258 	hisi_zip_open_sva_prefetch(qm);  in hisi_zip_pf_probe_init()
1259 	hisi_qm_dev_err_init(qm);  in hisi_zip_pf_probe_init()
1260 	hisi_zip_debug_regs_clear(qm);  in hisi_zip_pf_probe_init()
1262 	ret = hisi_zip_show_last_regs_init(qm);  in hisi_zip_pf_probe_init()
1264 		pci_err(qm->pdev, "Failed to init last word regs!\n");  in hisi_zip_pf_probe_init()
1269 static int zip_pre_store_cap_reg(struct hisi_qm *qm)  in zip_pre_store_cap_reg()  argument
1272 	struct pci_dev *pdev = qm->pdev;  in zip_pre_store_cap_reg()
1283 		zip_cap[i].cap_val = hisi_qm_get_cap_value(qm, zip_cap_query_info,  in zip_pre_store_cap_reg()
1284 				     i, qm->cap_ver);  in zip_pre_store_cap_reg()
1287 	qm->cap_tables.dev_cap_table = zip_cap;  in zip_pre_store_cap_reg()
1288 	qm->cap_tables.dev_cap_size = size;  in zip_pre_store_cap_reg()
1293 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)  in hisi_zip_qm_init()  argument
1298 	qm->pdev = pdev;  in hisi_zip_qm_init()
1299 	qm->mode = uacce_mode;  in hisi_zip_qm_init()
1300 	qm->sqe_size = HZIP_SQE_SIZE;  in hisi_zip_qm_init()
1301 	qm->dev_name = hisi_zip_name;  in hisi_zip_qm_init()
1303 	qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ?  in hisi_zip_qm_init()
1305 	if (qm->fun_type == QM_HW_PF) {  in hisi_zip_qm_init()
1306 		qm->qp_base = HZIP_PF_DEF_Q_BASE;  in hisi_zip_qm_init()
1307 		qm->qp_num = pf_q_num;  in hisi_zip_qm_init()
1308 		qm->debug.curr_qm_qp_num = pf_q_num;  in hisi_zip_qm_init()
1309 		qm->qm_list = &zip_devices;  in hisi_zip_qm_init()
1310 		qm->err_ini = &hisi_zip_err_ini;  in hisi_zip_qm_init()
1312 			set_bit(QM_MODULE_PARAM, &qm->misc_ctl);  in hisi_zip_qm_init()
1313 	} else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {  in hisi_zip_qm_init()
1315 		 * have no way to get qm configure in VM in v1 hardware,  in hisi_zip_qm_init()
1321 		qm->qp_base = HZIP_PF_DEF_Q_NUM;  in hisi_zip_qm_init()
1322 		qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM;  in hisi_zip_qm_init()
1325 	ret = hisi_qm_init(qm);  in hisi_zip_qm_init()
1327 		pci_err(qm->pdev, "Failed to init zip qm configures!\n");  in hisi_zip_qm_init()
1332 	ret = zip_pre_store_cap_reg(qm);  in hisi_zip_qm_init()
1334 		pci_err(qm->pdev, "Failed to pre-store capability registers!\n");  in hisi_zip_qm_init()
1338 	alg_msk = qm->cap_tables.dev_cap_table[ZIP_ALG_BITMAP].cap_val;  in hisi_zip_qm_init()
1339 	ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs));  in hisi_zip_qm_init()
1341 		pci_err(qm->pdev, "Failed to set zip algs!\n");  in hisi_zip_qm_init()
1345 	ret = hisi_dae_set_alg(qm);  in hisi_zip_qm_init()
1352 	hisi_qm_uninit(qm);  in hisi_zip_qm_init()
1356 static void hisi_zip_qm_uninit(struct hisi_qm *qm)  in hisi_zip_qm_uninit()  argument
1358 	hisi_qm_uninit(qm);  in hisi_zip_qm_uninit()
1364 	struct hisi_qm *qm = &hisi_zip->qm;  in hisi_zip_probe_init()  local
1367 	if (qm->fun_type == QM_HW_PF) {  in hisi_zip_probe_init()
1372 		if (qm->ver >= QM_HW_V3) {  in hisi_zip_probe_init()
1377 			qm->type_rate = type_rate;  in hisi_zip_probe_init()
1384 static void hisi_zip_probe_uninit(struct hisi_qm *qm)  in hisi_zip_probe_uninit()  argument
1386 	if (qm->fun_type == QM_HW_VF)  in hisi_zip_probe_uninit()
1389 	hisi_zip_show_last_regs_uninit(qm);  in hisi_zip_probe_uninit()
1390 	hisi_zip_close_sva_prefetch(qm);  in hisi_zip_probe_uninit()
1391 	hisi_qm_dev_err_uninit(qm);  in hisi_zip_probe_uninit()
1397 	struct hisi_qm *qm;  in hisi_zip_probe()  local
1404 	qm = &hisi_zip->qm;  in hisi_zip_probe()
1406 	ret = hisi_zip_qm_init(qm, pdev);  in hisi_zip_probe()
1408 		pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret);  in hisi_zip_probe()
1418 	ret = hisi_qm_start(qm);  in hisi_zip_probe()
1422 	ret = hisi_zip_debugfs_init(qm);  in hisi_zip_probe()
1426 	hisi_qm_add_list(qm, &zip_devices);  in hisi_zip_probe()
1427 	ret = hisi_qm_alg_register(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF);  in hisi_zip_probe()
1433 	if (qm->uacce) {  in hisi_zip_probe()
1434 		ret = uacce_register(qm->uacce);  in hisi_zip_probe()
1441 	if (qm->fun_type == QM_HW_PF && vfs_num > 0) {  in hisi_zip_probe()
1447 	hisi_qm_pm_init(qm);  in hisi_zip_probe()
1452 	hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF);  in hisi_zip_probe()
1455 	hisi_qm_del_list(qm, &zip_devices);  in hisi_zip_probe()
1456 	hisi_zip_debugfs_exit(qm);  in hisi_zip_probe()
1457 	hisi_qm_stop(qm, QM_NORMAL);  in hisi_zip_probe()
1460 	hisi_zip_probe_uninit(qm);  in hisi_zip_probe()
1463 	hisi_zip_qm_uninit(qm);  in hisi_zip_probe()
1470 	struct hisi_qm *qm = pci_get_drvdata(pdev);  in hisi_zip_remove()  local
1472 	hisi_qm_pm_uninit(qm);  in hisi_zip_remove()
1473 	hisi_qm_wait_task_finish(qm, &zip_devices);  in hisi_zip_remove()
1474 	hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF);  in hisi_zip_remove()
1475 	hisi_qm_del_list(qm, &zip_devices);  in hisi_zip_remove()
1477 	if (qm->fun_type == QM_HW_PF && qm->vfs_num)  in hisi_zip_remove()
1480 	hisi_zip_debugfs_exit(qm);  in hisi_zip_remove()
1481 	hisi_qm_stop(qm, QM_NORMAL);  in hisi_zip_remove()
1482 	hisi_zip_probe_uninit(qm);  in hisi_zip_remove()
1483 	hisi_zip_qm_uninit(qm);  in hisi_zip_remove()