55 static inline bool dae_is_support(struct hisi_qm *qm)  in dae_is_support()  argument
57 	if (test_bit(QM_SUPPORT_DAE, &qm->caps))  in dae_is_support()
63 int hisi_dae_set_user_domain(struct hisi_qm *qm)  in hisi_dae_set_user_domain()  argument
68 	if (!dae_is_support(qm))  in hisi_dae_set_user_domain()
71 	val = readl(qm->io_base + DAE_MEM_START_OFFSET);  in hisi_dae_set_user_domain()
73 	writel(val, qm->io_base + DAE_MEM_START_OFFSET);  in hisi_dae_set_user_domain()
74 	ret = readl_relaxed_poll_timeout(qm->io_base + DAE_MEM_DONE_OFFSET, val,  in hisi_dae_set_user_domain()
78 		pci_err(qm->pdev, "failed to init dae memory!\n");  in hisi_dae_set_user_domain()
83 int hisi_dae_set_alg(struct hisi_qm *qm)  in hisi_dae_set_alg()  argument
87 	if (!dae_is_support(qm))  in hisi_dae_set_alg()
90 	if (!qm->uacce)  in hisi_dae_set_alg()
93 	len = strlen(qm->uacce->algs);  in hisi_dae_set_alg()
96 		pci_err(qm->pdev, "algorithm name is too long!\n");  in hisi_dae_set_alg()
101 		strcat((char *)qm->uacce->algs, "\n");  in hisi_dae_set_alg()
103 	strcat((char *)qm->uacce->algs, DAE_ALG_NAME);  in hisi_dae_set_alg()
108 static void hisi_dae_master_ooo_ctrl(struct hisi_qm *qm, bool enable)  in hisi_dae_master_ooo_ctrl()  argument
112 	axi_val = readl(qm->io_base + DAE_AXI_CFG_OFFSET);  in hisi_dae_master_ooo_ctrl()
121 	writel(axi_val, qm->io_base + DAE_AXI_CFG_OFFSET);  in hisi_dae_master_ooo_ctrl()
122 	writel(err_val, qm->io_base + DAE_ERR_SHUTDOWN_OFFSET);  in hisi_dae_master_ooo_ctrl()
125 void hisi_dae_hw_error_enable(struct hisi_qm *qm)  in hisi_dae_hw_error_enable()  argument
127 	if (!dae_is_support(qm))  in hisi_dae_hw_error_enable()
131 	writel(DAE_ERR_ENABLE_MASK, qm->io_base + DAE_ERR_SOURCE_OFFSET);  in hisi_dae_hw_error_enable()
134 	writel(DAE_ERR_CE_MASK, qm->io_base + DAE_ERR_CE_OFFSET);  in hisi_dae_hw_error_enable()
135 	writel(DAE_ERR_NFE_MASK, qm->io_base + DAE_ERR_NFE_OFFSET);  in hisi_dae_hw_error_enable()
136 	writel(DAE_ERR_FE_MASK, qm->io_base + DAE_ERR_FE_OFFSET);  in hisi_dae_hw_error_enable()
138 	hisi_dae_master_ooo_ctrl(qm, true);  in hisi_dae_hw_error_enable()
141 	writel(DAE_ERR_ENABLE_MASK, qm->io_base + DAE_ERR_ENABLE_OFFSET);  in hisi_dae_hw_error_enable()
144 void hisi_dae_hw_error_disable(struct hisi_qm *qm)  in hisi_dae_hw_error_disable()  argument
146 	if (!dae_is_support(qm))  in hisi_dae_hw_error_disable()
149 	writel(0, qm->io_base + DAE_ERR_ENABLE_OFFSET);  in hisi_dae_hw_error_disable()
150 	hisi_dae_master_ooo_ctrl(qm, false);  in hisi_dae_hw_error_disable()
153 static u32 hisi_dae_get_hw_err_status(struct hisi_qm *qm)  in hisi_dae_get_hw_err_status()  argument
155 	return readl(qm->io_base + DAE_ERR_STATUS_OFFSET);  in hisi_dae_get_hw_err_status()
158 static void hisi_dae_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)  in hisi_dae_clear_hw_err_status()  argument
160 	if (!dae_is_support(qm))  in hisi_dae_clear_hw_err_status()
163 	writel(err_sts, qm->io_base + DAE_ERR_SOURCE_OFFSET);  in hisi_dae_clear_hw_err_status()
166 static void hisi_dae_disable_error_report(struct hisi_qm *qm, u32 err_type)  in hisi_dae_disable_error_report()  argument
168 	writel(DAE_ERR_NFE_MASK & (~err_type), qm->io_base + DAE_ERR_NFE_OFFSET);  in hisi_dae_disable_error_report()
171 static void hisi_dae_log_hw_error(struct hisi_qm *qm, u32 err_type)  in hisi_dae_log_hw_error()  argument
174 	struct device *dev = &qm->pdev->dev;  in hisi_dae_log_hw_error()
187 			ecc_info = readl(qm->io_base + DAE_ECC_INFO_OFFSET);  in hisi_dae_log_hw_error()
193 enum acc_err_result hisi_dae_get_err_result(struct hisi_qm *qm)  in hisi_dae_get_err_result()  argument
197 	if (!dae_is_support(qm))  in hisi_dae_get_err_result()
200 	err_status = hisi_dae_get_hw_err_status(qm);  in hisi_dae_get_err_result()
204 	hisi_dae_log_hw_error(qm, err_status);  in hisi_dae_get_err_result()
208 		hisi_dae_disable_error_report(qm, err_status);  in hisi_dae_get_err_result()
211 	hisi_dae_clear_hw_err_status(qm, err_status);  in hisi_dae_get_err_result()
216 bool hisi_dae_dev_is_abnormal(struct hisi_qm *qm)  in hisi_dae_dev_is_abnormal()  argument
220 	if (!dae_is_support(qm))  in hisi_dae_dev_is_abnormal()
223 	err_status = hisi_dae_get_hw_err_status(qm);  in hisi_dae_dev_is_abnormal()
230 int hisi_dae_close_axi_master_ooo(struct hisi_qm *qm)  in hisi_dae_close_axi_master_ooo()  argument
235 	if (!dae_is_support(qm))  in hisi_dae_close_axi_master_ooo()
238 	val = readl(qm->io_base + DAE_AM_CTRL_GLOBAL_OFFSET);  in hisi_dae_close_axi_master_ooo()
240 	writel(val, qm->io_base + DAE_AM_CTRL_GLOBAL_OFFSET);  in hisi_dae_close_axi_master_ooo()
242 	ret = readl_relaxed_poll_timeout(qm->io_base + DAE_AM_RETURN_OFFSET,  in hisi_dae_close_axi_master_ooo()
246 		dev_err(&qm->pdev->dev, "failed to close dae axi ooo!\n");  in hisi_dae_close_axi_master_ooo()
251 void hisi_dae_open_axi_master_ooo(struct hisi_qm *qm)  in hisi_dae_open_axi_master_ooo()  argument
255 	if (!dae_is_support(qm))  in hisi_dae_open_axi_master_ooo()
258 	val = readl(qm->io_base + DAE_AXI_CFG_OFFSET);  in hisi_dae_open_axi_master_ooo()
260 	writel(val & ~DAE_AXI_SHUTDOWN_EN_MASK, qm->io_base + DAE_AXI_CFG_OFFSET);  in hisi_dae_open_axi_master_ooo()
261 	writel(val | DAE_AXI_SHUTDOWN_EN_MASK, qm->io_base + DAE_AXI_CFG_OFFSET);  in hisi_dae_open_axi_master_ooo()