Lines Matching full:qm
334 struct hisi_qm *qm = s->private; in sec_diff_regs_show() local
336 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in sec_diff_regs_show()
422 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) in sec_get_alg_bitmap() argument
426 cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val; in sec_get_alg_bitmap()
427 cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val; in sec_get_alg_bitmap()
452 static void sec_set_endian(struct hisi_qm *qm) in sec_set_endian() argument
456 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
464 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
467 static void sec_engine_sva_config(struct hisi_qm *qm) in sec_engine_sva_config() argument
471 if (qm->ver > QM_HW_V2) { in sec_engine_sva_config()
472 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
475 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
478 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
482 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
485 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
488 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
490 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
493 if (qm->use_sva) in sec_engine_sva_config()
497 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
502 static void sec_open_sva_prefetch(struct hisi_qm *qm) in sec_open_sva_prefetch() argument
507 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) in sec_open_sva_prefetch()
511 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); in sec_open_sva_prefetch()
513 writel(val, qm->io_base + SEC_PREFETCH_CFG); in sec_open_sva_prefetch()
515 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG, in sec_open_sva_prefetch()
519 pci_err(qm->pdev, "failed to open sva prefetch\n"); in sec_open_sva_prefetch()
522 static void sec_close_sva_prefetch(struct hisi_qm *qm) in sec_close_sva_prefetch() argument
527 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) in sec_close_sva_prefetch()
530 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); in sec_close_sva_prefetch()
532 writel(val, qm->io_base + SEC_PREFETCH_CFG); in sec_close_sva_prefetch()
534 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS, in sec_close_sva_prefetch()
538 pci_err(qm->pdev, "failed to close sva prefetch\n"); in sec_close_sva_prefetch()
541 static void sec_enable_clock_gate(struct hisi_qm *qm) in sec_enable_clock_gate() argument
545 if (qm->ver < QM_HW_V3) in sec_enable_clock_gate()
548 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
550 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
552 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG); in sec_enable_clock_gate()
554 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG); in sec_enable_clock_gate()
556 val = readl(qm->io_base + SEC_CORE_AUTO_GATE); in sec_enable_clock_gate()
558 writel(val, qm->io_base + SEC_CORE_AUTO_GATE); in sec_enable_clock_gate()
561 static void sec_disable_clock_gate(struct hisi_qm *qm) in sec_disable_clock_gate() argument
566 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
568 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
571 static int sec_engine_init(struct hisi_qm *qm) in sec_engine_init() argument
577 sec_disable_clock_gate(qm); in sec_engine_init()
579 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG); in sec_engine_init()
581 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG, in sec_engine_init()
585 pci_err(qm->pdev, "fail to init sec mem\n"); in sec_engine_init()
589 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
591 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
593 sec_engine_sva_config(qm); in sec_engine_init()
596 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); in sec_engine_init()
598 reg = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CORE_ENABLE_BITMAP, qm->cap_ver); in sec_engine_init()
599 writel(reg, qm->io_base + SEC_SAA_EN_REG); in sec_engine_init()
601 if (qm->ver < QM_HW_V3) { in sec_engine_init()
604 qm->io_base + SEC_BD_ERR_CHK_EN_REG0); in sec_engine_init()
608 qm->io_base + SEC_BD_ERR_CHK_EN_REG1); in sec_engine_init()
610 qm->io_base + SEC_BD_ERR_CHK_EN_REG3); in sec_engine_init()
614 sec_set_endian(qm); in sec_engine_init()
616 sec_enable_clock_gate(qm); in sec_engine_init()
621 static int sec_set_user_domain_and_cache(struct hisi_qm *qm) in sec_set_user_domain_and_cache() argument
623 /* qm user domain */ in sec_set_user_domain_and_cache()
624 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1); in sec_set_user_domain_and_cache()
625 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
626 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1); in sec_set_user_domain_and_cache()
627 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
628 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
630 /* qm cache */ in sec_set_user_domain_and_cache()
631 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG); in sec_set_user_domain_and_cache()
632 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
635 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG); in sec_set_user_domain_and_cache()
636 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); in sec_set_user_domain_and_cache()
641 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL); in sec_set_user_domain_and_cache()
643 return sec_engine_init(qm); in sec_set_user_domain_and_cache()
647 static void sec_debug_regs_clear(struct hisi_qm *qm) in sec_debug_regs_clear() argument
652 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_debug_regs_clear()
654 readl(qm->io_base + sec_dfx_regs[i].offset); in sec_debug_regs_clear()
657 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_debug_regs_clear()
659 hisi_qm_debug_regs_clear(qm); in sec_debug_regs_clear()
662 static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable) in sec_master_ooo_ctrl() argument
666 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
669 val2 = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_master_ooo_ctrl()
670 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in sec_master_ooo_ctrl()
676 if (qm->ver > QM_HW_V2) in sec_master_ooo_ctrl()
677 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL); in sec_master_ooo_ctrl()
679 writel(val1, qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
682 static void sec_hw_error_enable(struct hisi_qm *qm) in sec_hw_error_enable() argument
686 if (qm->ver == QM_HW_V1) { in sec_hw_error_enable()
687 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_enable()
688 pci_info(qm->pdev, "V1 not support hw error handle\n"); in sec_hw_error_enable()
692 ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver); in sec_hw_error_enable()
693 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); in sec_hw_error_enable()
696 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_SOURCE); in sec_hw_error_enable()
699 writel(ce, qm->io_base + SEC_RAS_CE_REG); in sec_hw_error_enable()
700 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG); in sec_hw_error_enable()
701 writel(nfe, qm->io_base + SEC_RAS_NFE_REG); in sec_hw_error_enable()
704 sec_master_ooo_ctrl(qm, true); in sec_hw_error_enable()
707 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_enable()
710 static void sec_hw_error_disable(struct hisi_qm *qm) in sec_hw_error_disable() argument
713 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_disable()
716 sec_master_ooo_ctrl(qm, false); in sec_hw_error_disable()
719 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG); in sec_hw_error_disable()
720 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG); in sec_hw_error_disable()
721 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG); in sec_hw_error_disable()
724 static u32 sec_clear_enable_read(struct hisi_qm *qm) in sec_clear_enable_read() argument
726 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & in sec_clear_enable_read()
730 static int sec_clear_enable_write(struct hisi_qm *qm, u32 val) in sec_clear_enable_write() argument
737 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & in sec_clear_enable_write()
739 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_clear_enable_write()
749 struct hisi_qm *qm = file->qm; in sec_debug_read() local
753 ret = hisi_qm_get_dfx_access(qm); in sec_debug_read()
761 val = sec_clear_enable_read(qm); in sec_debug_read()
769 hisi_qm_put_dfx_access(qm); in sec_debug_read()
775 hisi_qm_put_dfx_access(qm); in sec_debug_read()
784 struct hisi_qm *qm = file->qm; in sec_debug_write() local
803 ret = hisi_qm_get_dfx_access(qm); in sec_debug_write()
811 ret = sec_clear_enable_write(qm, val); in sec_debug_write()
824 hisi_qm_put_dfx_access(qm); in sec_debug_write()
866 struct hisi_qm *qm = s->private; in sec_cap_regs_show() local
869 size = qm->cap_tables.qm_cap_size; in sec_cap_regs_show()
871 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name, in sec_cap_regs_show()
872 qm->cap_tables.qm_cap_table[i].cap_val); in sec_cap_regs_show()
874 size = qm->cap_tables.dev_cap_size; in sec_cap_regs_show()
876 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name, in sec_cap_regs_show()
877 qm->cap_tables.dev_cap_table[i].cap_val); in sec_cap_regs_show()
884 static int sec_core_debug_init(struct hisi_qm *qm) in sec_core_debug_init() argument
886 struct dfx_diff_registers *sec_regs = qm->debug.acc_diff_regs; in sec_core_debug_init()
887 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); in sec_core_debug_init()
888 struct device *dev = &qm->pdev->dev; in sec_core_debug_init()
894 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root); in sec_core_debug_init()
902 regset->base = qm->io_base; in sec_core_debug_init()
905 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) in sec_core_debug_init()
907 if (qm->fun_type == QM_HW_PF && sec_regs) in sec_core_debug_init()
909 qm, &sec_diff_regs_fops); in sec_core_debug_init()
919 qm->debug.debug_root, qm, &sec_cap_regs_fops); in sec_core_debug_init()
924 static int sec_debug_init(struct hisi_qm *qm) in sec_debug_init() argument
926 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); in sec_debug_init()
929 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) { in sec_debug_init()
933 sec->debug.files[i].qm = qm; in sec_debug_init()
936 qm->debug.debug_root, in sec_debug_init()
942 return sec_core_debug_init(qm); in sec_debug_init()
945 static int sec_debugfs_init(struct hisi_qm *qm) in sec_debugfs_init() argument
947 struct device *dev = &qm->pdev->dev; in sec_debugfs_init()
950 ret = hisi_qm_regs_debugfs_init(qm, sec_diff_regs, ARRAY_SIZE(sec_diff_regs)); in sec_debugfs_init()
956 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), in sec_debugfs_init()
958 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET; in sec_debugfs_init()
959 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN; in sec_debugfs_init()
961 hisi_qm_debug_init(qm); in sec_debugfs_init()
963 ret = sec_debug_init(qm); in sec_debugfs_init()
970 debugfs_remove_recursive(qm->debug.debug_root); in sec_debugfs_init()
971 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs)); in sec_debugfs_init()
975 static void sec_debugfs_exit(struct hisi_qm *qm) in sec_debugfs_exit() argument
977 debugfs_remove_recursive(qm->debug.debug_root); in sec_debugfs_exit()
979 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs)); in sec_debugfs_exit()
982 static int sec_show_last_regs_init(struct hisi_qm *qm) in sec_show_last_regs_init() argument
984 struct qm_debug *debug = &qm->debug; in sec_show_last_regs_init()
993 debug->last_words[i] = readl_relaxed(qm->io_base + in sec_show_last_regs_init()
999 static void sec_show_last_regs_uninit(struct hisi_qm *qm) in sec_show_last_regs_uninit() argument
1001 struct qm_debug *debug = &qm->debug; in sec_show_last_regs_uninit()
1003 if (qm->fun_type == QM_HW_VF || !debug->last_words) in sec_show_last_regs_uninit()
1010 static void sec_show_last_dfx_regs(struct hisi_qm *qm) in sec_show_last_dfx_regs() argument
1012 struct qm_debug *debug = &qm->debug; in sec_show_last_dfx_regs()
1013 struct pci_dev *pdev = qm->pdev; in sec_show_last_dfx_regs()
1017 if (qm->fun_type == QM_HW_VF || !debug->last_words) in sec_show_last_dfx_regs()
1022 val = readl_relaxed(qm->io_base + sec_dfx_regs[i].offset); in sec_show_last_dfx_regs()
1029 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts) in sec_log_hw_error() argument
1032 struct device *dev = &qm->pdev->dev; in sec_log_hw_error()
1041 err_val = readl(qm->io_base + in sec_log_hw_error()
1052 static u32 sec_get_hw_err_status(struct hisi_qm *qm) in sec_get_hw_err_status() argument
1054 return readl(qm->io_base + SEC_CORE_INT_STATUS); in sec_get_hw_err_status()
1057 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) in sec_clear_hw_err_status() argument
1059 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE); in sec_clear_hw_err_status()
1062 static void sec_disable_error_report(struct hisi_qm *qm, u32 err_type) in sec_disable_error_report() argument
1066 nfe_mask = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); in sec_disable_error_report()
1067 writel(nfe_mask & (~err_type), qm->io_base + SEC_RAS_NFE_REG); in sec_disable_error_report()
1070 static void sec_open_axi_master_ooo(struct hisi_qm *qm) in sec_open_axi_master_ooo() argument
1074 val = readl(qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1075 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1076 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1079 static enum acc_err_result sec_get_err_result(struct hisi_qm *qm) in sec_get_err_result() argument
1083 err_status = sec_get_hw_err_status(qm); in sec_get_err_result()
1085 if (err_status & qm->err_info.ecc_2bits_mask) in sec_get_err_result()
1086 qm->err_status.is_dev_ecc_mbit = true; in sec_get_err_result()
1087 sec_log_hw_error(qm, err_status); in sec_get_err_result()
1089 if (err_status & qm->err_info.dev_reset_mask) { in sec_get_err_result()
1091 sec_disable_error_report(qm, err_status); in sec_get_err_result()
1094 sec_clear_hw_err_status(qm, err_status); in sec_get_err_result()
1100 static bool sec_dev_is_abnormal(struct hisi_qm *qm) in sec_dev_is_abnormal() argument
1104 err_status = sec_get_hw_err_status(qm); in sec_dev_is_abnormal()
1105 if (err_status & qm->err_info.dev_shutdown_mask) in sec_dev_is_abnormal()
1111 static void sec_err_info_init(struct hisi_qm *qm) in sec_err_info_init() argument
1113 struct hisi_qm_err_info *err_info = &qm->err_info; in sec_err_info_init()
1116 err_info->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1117 err_info->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1119 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1120 SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1121 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1122 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1123 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1124 SEC_QM_RESET_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1125 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1126 SEC_RESET_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1148 struct hisi_qm *qm = &sec->qm; in sec_pf_probe_init() local
1151 ret = sec_set_user_domain_and_cache(qm); in sec_pf_probe_init()
1155 sec_open_sva_prefetch(qm); in sec_pf_probe_init()
1156 hisi_qm_dev_err_init(qm); in sec_pf_probe_init()
1157 sec_debug_regs_clear(qm); in sec_pf_probe_init()
1158 ret = sec_show_last_regs_init(qm); in sec_pf_probe_init()
1160 pci_err(qm->pdev, "Failed to init last word regs!\n"); in sec_pf_probe_init()
1165 static int sec_pre_store_cap_reg(struct hisi_qm *qm) in sec_pre_store_cap_reg() argument
1168 struct pci_dev *pdev = qm->pdev; in sec_pre_store_cap_reg()
1179 sec_cap[i].cap_val = hisi_qm_get_cap_value(qm, sec_cap_query_info, in sec_pre_store_cap_reg()
1180 i, qm->cap_ver); in sec_pre_store_cap_reg()
1183 qm->cap_tables.dev_cap_table = sec_cap; in sec_pre_store_cap_reg()
1184 qm->cap_tables.dev_cap_size = size; in sec_pre_store_cap_reg()
1189 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) in sec_qm_init() argument
1194 qm->pdev = pdev; in sec_qm_init()
1195 qm->mode = uacce_mode; in sec_qm_init()
1196 qm->sqe_size = SEC_SQE_SIZE; in sec_qm_init()
1197 qm->dev_name = sec_name; in sec_qm_init()
1199 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ? in sec_qm_init()
1201 if (qm->fun_type == QM_HW_PF) { in sec_qm_init()
1202 qm->qp_base = SEC_PF_DEF_Q_BASE; in sec_qm_init()
1203 qm->qp_num = pf_q_num; in sec_qm_init()
1204 qm->debug.curr_qm_qp_num = pf_q_num; in sec_qm_init()
1205 qm->qm_list = &sec_devices; in sec_qm_init()
1206 qm->err_ini = &sec_err_ini; in sec_qm_init()
1208 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); in sec_qm_init()
1209 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { in sec_qm_init()
1211 * have no way to get qm configure in VM in v1 hardware, in sec_qm_init()
1216 qm->qp_base = SEC_PF_DEF_Q_NUM; in sec_qm_init()
1217 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM; in sec_qm_init()
1220 ret = hisi_qm_init(qm); in sec_qm_init()
1222 pci_err(qm->pdev, "Failed to init sec qm configures!\n"); in sec_qm_init()
1227 ret = sec_pre_store_cap_reg(qm); in sec_qm_init()
1229 pci_err(qm->pdev, "Failed to pre-store capability registers!\n"); in sec_qm_init()
1230 hisi_qm_uninit(qm); in sec_qm_init()
1233 alg_msk = sec_get_alg_bitmap(qm, SEC_ALG_BITMAP_HIGH, SEC_ALG_BITMAP_LOW); in sec_qm_init()
1234 ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs)); in sec_qm_init()
1236 pci_err(qm->pdev, "Failed to set sec algs!\n"); in sec_qm_init()
1237 hisi_qm_uninit(qm); in sec_qm_init()
1243 static void sec_qm_uninit(struct hisi_qm *qm) in sec_qm_uninit() argument
1245 hisi_qm_uninit(qm); in sec_qm_uninit()
1251 struct hisi_qm *qm = &sec->qm; in sec_probe_init() local
1254 if (qm->fun_type == QM_HW_PF) { in sec_probe_init()
1259 if (qm->ver >= QM_HW_V3) { in sec_probe_init()
1261 qm->type_rate = type_rate; in sec_probe_init()
1268 static void sec_probe_uninit(struct hisi_qm *qm) in sec_probe_uninit() argument
1270 if (qm->fun_type == QM_HW_VF) in sec_probe_uninit()
1273 sec_debug_regs_clear(qm); in sec_probe_uninit()
1274 sec_show_last_regs_uninit(qm); in sec_probe_uninit()
1275 sec_close_sva_prefetch(qm); in sec_probe_uninit()
1276 hisi_qm_dev_err_uninit(qm); in sec_probe_uninit()
1282 struct device *dev = &sec->qm.pdev->dev; in sec_iommu_used_check()
1299 struct hisi_qm *qm; in sec_probe() local
1306 qm = &sec->qm; in sec_probe()
1307 ret = sec_qm_init(qm, pdev); in sec_probe()
1309 pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret); in sec_probe()
1322 ret = hisi_qm_start(qm); in sec_probe()
1324 pci_err(pdev, "Failed to start sec qm!\n"); in sec_probe()
1328 ret = sec_debugfs_init(qm); in sec_probe()
1332 hisi_qm_add_list(qm, &sec_devices); in sec_probe()
1333 ret = hisi_qm_alg_register(qm, &sec_devices, ctx_q_num); in sec_probe()
1339 if (qm->uacce) { in sec_probe()
1340 ret = uacce_register(qm->uacce); in sec_probe()
1347 if (qm->fun_type == QM_HW_PF && vfs_num) { in sec_probe()
1353 hisi_qm_pm_init(qm); in sec_probe()
1358 hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num); in sec_probe()
1360 hisi_qm_del_list(qm, &sec_devices); in sec_probe()
1361 sec_debugfs_exit(qm); in sec_probe()
1362 hisi_qm_stop(qm, QM_NORMAL); in sec_probe()
1364 sec_probe_uninit(qm); in sec_probe()
1366 sec_qm_uninit(qm); in sec_probe()
1372 struct hisi_qm *qm = pci_get_drvdata(pdev); in sec_remove() local
1374 hisi_qm_pm_uninit(qm); in sec_remove()
1375 hisi_qm_wait_task_finish(qm, &sec_devices); in sec_remove()
1376 hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num); in sec_remove()
1377 hisi_qm_del_list(qm, &sec_devices); in sec_remove()
1379 if (qm->fun_type == QM_HW_PF && qm->vfs_num) in sec_remove()
1382 sec_debugfs_exit(qm); in sec_remove()
1384 (void)hisi_qm_stop(qm, QM_NORMAL); in sec_remove()
1385 sec_probe_uninit(qm); in sec_remove()
1387 sec_qm_uninit(qm); in sec_remove()