Lines Matching +full:co +full:- +full:processors
1 # SPDX-License-Identifier: GPL-2.0-only
8 processors. This option alone does not add any kernel code.
20 Some VIA processors come with an integrated crypto engine
39 called padlock-aes.
50 Available in VIA C7 and newer processors.
53 called padlock-sha.
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
65 will be called geode-aes.
87 - A pkey base and API kernel module (pkey.ko) which offers the
89 and the sysfs API and the in-kernel API to the crypto cipher
91 - A pkey pckmo kernel module (pkey-pckmo.ko) which is automatically
94 - A pkey CCA kernel module (pkey-cca.ko) which is automatically
96 - A pkey EP11 kernel module (pkey-ep11.ko) which is automatically
98 - A pkey UV kernel module (pkey-uv.ko) which is automatically
197 and uses triple-DES to generate secure random numbers like the
198 ANSI X9.17 standard. User-space programs access the
199 pseudo-random-number device through the char device /dev/prandom.
256 The Freescale SEC is present on PowerQUICC 'E' processors, such
299 This option provides the kernel-side support for the TRNG hardware
306 OMAP processors have various crypto HW accelerators. Select this if
321 OMAP processors have MD5/SHA1/SHA2 hw accelerator. Select this if you
335 OMAP processors have AES module accelerator. Select this if you
345 OMAP processors have DES/3DES module accelerator. Select this if you
369 This driver provides kernel-side support through the
374 module will be called exynos-rng.
399 needed for small and zero-size messages.
408 coprocessor that is in IBM PowerPC P7+ or later processors. This
421 Some Atmel processors can combine the AES and SHA hw accelerators
435 Some Atmel processors have AES hw accelerator.
440 will be called atmel-aes.
448 Some Atmel processors have DES/TDES hw accelerator.
453 will be called atmel-tdes.
460 Some Atmel processors have SHA1/SHA224/SHA256/SHA384/SHA512
466 will be called atmel-sha.
484 will be called atmel-ecc.
499 will be called atmel-sha204a.
523 co-processor on the die.
526 will be called mxs-dcp.
578 (default), hashes-only, or skciphers-only.
581 multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
585 algorithms, sharing the load with the CPU. Enabling skciphers-only
595 - AES (CBC, CTR, ECB, XTS)
596 - 3DES (CBC, ECB)
597 - DES (CBC, ECB)
598 - SHA1, HMAC-SHA1
599 - SHA256, HMAC-SHA256
602 bool "Symmetric-key ciphers only"
605 Enable symmetric-key ciphers only:
606 - AES (CBC, CTR, ECB, XTS)
607 - 3DES (ECB, CBC)
608 - DES (ECB, CBC)
615 - SHA1, HMAC-SHA1
616 - SHA256, HMAC-SHA256
623 - authenc()
624 - ccm(aes)
625 - rfc4309(ccm(aes))
638 Considering the 256-bit ciphers, software is 2-3 times faster than
639 qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
640 With 128-bit keys, the break-even point would be around 1024-bytes.
643 cost in CPU usage. The minimum recommended setting is 16-bytes
644 (1 AES block), since AES-GCM will fail if you set it lower.
647 Note that 192-bit keys are not supported by the hardware and are
661 module will be called qcom-rng. If unsure, say N.
728 Xilinx ZynqMP has AES-GCM engine used for symmetric key
781 This driver interfaces with the SafeXcel EIP-97 and EIP-197 cryptographic
785 Additionally, it accelerates combined AES-CBC/HMAC-SHA AEAD operations.
788 tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
801 Enables the driver for the on-chip crypto accelerator
807 tristate "Support for ARM TrustZone CryptoCell family of security processors"
829 TrustZone CryptoCell family of processors. Currently the