Lines Matching +full:0 +full:xf80000
21 #define REVISION_MASK 0xF
24 #define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F
25 #define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA
33 #define DRA7_EFUSE_NOM_MPU_OPP BIT(0)
38 #define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C
39 #define OMAP3_CONTROL_IDCODE 0x4830A204
40 #define OMAP34xx_ProdID_SKUID 0x4830A20C
41 #define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270)
47 #define AM625_SUPPORT_K_MPU_OPP BIT(0)
69 #define AM62A7_SUPPORT_N_MPU_OPP BIT(0)
77 #define AM62P5_SUPPORT_O_MPU_OPP BIT(0)
95 #define TI_QUIRK_SYSCON_MAY_BE_MISSING 0x1
97 #define TI_QUIRK_SYSCON_IS_SINGLE_REG 0x2
215 .efuse_offset = 0x07fc,
216 .efuse_mask = 0x1fff,
217 .rev_offset = 0x600,
224 .efuse_offset = 0x0610,
225 .efuse_mask = 0x3f,
226 .rev_offset = 0x600,
232 .efuse_offset = 0x020c,
233 .efuse_mask = 0xf80000,
235 .rev_offset = 0x204,
241 * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
242 * Control OMAP Status Register 15:0 (Address 0x4800 244C)
250 * Register 0x4830A20C [ProdID.SKUID] [0:3]
251 * 0x0 for normal 600/430MHz device.
252 * 0x8 for 720/520MHz device.
268 * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
269 * Control Device Status Register 15:0 (Address 0x4800 244C)
273 * 0 800/600 MHz
277 * There is no 0x4830A20C [ProdID.SKUID] register (exists but
278 * seems to always read as 0).
302 .efuse_shift = 0,
303 .efuse_mask = 0,
310 { .family = "AM62X", .revision = "SR1.0" },
311 { .family = "AM62AX", .revision = "SR1.0" },
312 { .family = "AM62PX", .revision = "SR1.0" },
318 .efuse_offset = 0x0018,
319 .efuse_mask = 0x07c0,
320 .efuse_shift = 0x6,
327 .efuse_offset = 0x0,
328 .efuse_mask = 0x07c0,
329 .efuse_shift = 0x6,
335 .efuse_offset = 0x0,
336 .efuse_mask = 0x07c0,
337 .efuse_shift = 0x6,
359 ret = regmap_read(opp_data->syscon, 0x0, &efuse); in ti_cpufreq_get_efuse()
383 return 0; in ti_cpufreq_get_efuse()
402 * 0x1 here. This way we avoid re using the same register in ti_cpufreq_get_rev()
406 *revision_value = 0x1; in ti_cpufreq_get_rev()
432 return 0; in ti_cpufreq_get_rev()
448 return 0; in ti_cpufreq_setup_syscon_register()
499 opp_data->cpu_dev = get_cpu_device(0); in ti_cpufreq_probe()
519 * 0 - SoC Revision in ti_cpufreq_probe()
522 ret = ti_cpufreq_get_rev(opp_data, &version[0]); in ti_cpufreq_probe()
538 if (ret < 0) { in ti_cpufreq_probe()
546 platform_device_register_simple("cpufreq-dt", -1, NULL, 0); in ti_cpufreq_probe()
548 return 0; in ti_cpufreq_probe()
566 return 0; in ti_cpufreq_init()