1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk.h>
20 	struct clk *cpu_clk;
21 	struct clk *pllp_clk;
22 	struct clk *pllx_clk;
23 	struct clk *dfll_clk;
29 	struct clk *orig_parent;  in tegra124_cpu_switch_to_dfll()
32 	ret = clk_set_rate(priv->dfll_clk, clk_get_rate(priv->cpu_clk));  in tegra124_cpu_switch_to_dfll()
36 	orig_parent = clk_get_parent(priv->cpu_clk);  in tegra124_cpu_switch_to_dfll()
37 	clk_set_parent(priv->cpu_clk, priv->pllp_clk);  in tegra124_cpu_switch_to_dfll()
39 	ret = clk_prepare_enable(priv->dfll_clk);  in tegra124_cpu_switch_to_dfll()
43 	clk_set_parent(priv->cpu_clk, priv->dfll_clk);  in tegra124_cpu_switch_to_dfll()
48 	clk_set_parent(priv->cpu_clk, orig_parent);  in tegra124_cpu_switch_to_dfll()
62 		return -ENODEV;  in tegra124_cpufreq_probe()
64 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);  in tegra124_cpufreq_probe()
66 		return -ENOMEM;  in tegra124_cpufreq_probe()
70 		return -ENODEV;  in tegra124_cpufreq_probe()
72 	priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");  in tegra124_cpufreq_probe()
73 	if (IS_ERR(priv->cpu_clk))  in tegra124_cpufreq_probe()
74 		return PTR_ERR(priv->cpu_clk);  in tegra124_cpufreq_probe()
76 	priv->dfll_clk = of_clk_get_by_name(np, "dfll");  in tegra124_cpufreq_probe()
77 	if (IS_ERR(priv->dfll_clk)) {  in tegra124_cpufreq_probe()
78 		ret = PTR_ERR(priv->dfll_clk);  in tegra124_cpufreq_probe()
82 	priv->pllx_clk = of_clk_get_by_name(np, "pll_x");  in tegra124_cpufreq_probe()
83 	if (IS_ERR(priv->pllx_clk)) {  in tegra124_cpufreq_probe()
84 		ret = PTR_ERR(priv->pllx_clk);  in tegra124_cpufreq_probe()
88 	priv->pllp_clk = of_clk_get_by_name(np, "pll_p");  in tegra124_cpufreq_probe()
89 	if (IS_ERR(priv->pllp_clk)) {  in tegra124_cpufreq_probe()
90 		ret = PTR_ERR(priv->pllp_clk);  in tegra124_cpufreq_probe()
98 	cpufreq_dt_devinfo.name = "cpufreq-dt";  in tegra124_cpufreq_probe()
99 	cpufreq_dt_devinfo.parent = &pdev->dev;  in tegra124_cpufreq_probe()
101 	priv->cpufreq_dt_pdev =  in tegra124_cpufreq_probe()
103 	if (IS_ERR(priv->cpufreq_dt_pdev)) {  in tegra124_cpufreq_probe()
104 		ret = PTR_ERR(priv->cpufreq_dt_pdev);  in tegra124_cpufreq_probe()
113 	clk_put(priv->pllp_clk);  in tegra124_cpufreq_probe()
115 	clk_put(priv->pllx_clk);  in tegra124_cpufreq_probe()
117 	clk_put(priv->dfll_clk);  in tegra124_cpufreq_probe()
119 	clk_put(priv->cpu_clk);  in tegra124_cpufreq_probe()
131 	 * use during suspend and resume. So, switch the CPU clock source  in tegra124_cpufreq_suspend()
134 	err = clk_set_parent(priv->cpu_clk, priv->pllp_clk);  in tegra124_cpufreq_suspend()
140 	clk_disable_unprepare(priv->dfll_clk);  in tegra124_cpufreq_suspend()
151 	 * Warmboot code powers up the CPU with PLLP clock source.  in tegra124_cpufreq_resume()
152 	 * Enable DFLL clock and switch CPU clock source back to DFLL.  in tegra124_cpufreq_resume()
154 	err = clk_prepare_enable(priv->dfll_clk);  in tegra124_cpufreq_resume()
160 	err = clk_set_parent(priv->cpu_clk, priv->dfll_clk);  in tegra124_cpufreq_resume()
169 	clk_disable_unprepare(priv->dfll_clk);  in tegra124_cpufreq_resume()
182 	.driver.name	= "cpufreq-tegra124",
194 		return -ENODEV;  in tegra_cpufreq_init()
204 	pdev = platform_device_register_simple("cpufreq-tegra124", -1, NULL, 0);  in tegra_cpufreq_init()