22 #define NVMEM_MASK	0x7
25 #define SUN50I_A100_NVMEM_MASK	0xf
48 		return 0;  in sun50i_h6_efuse_xlate()
59 	case 0b100:  in sun50i_a100_efuse_xlate()
61 	case 0b010:  in sun50i_a100_efuse_xlate()
64 		return 0;  in sun50i_a100_efuse_xlate()
79  * returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best.
80  * 0 and 2 seem identical from the OPP tables' point of view.
85 	u32 value = 0;  in sun50i_h616_efuse_xlate()
87 	switch (speedbin & 0xffff) {  in sun50i_h616_efuse_xlate()
88 	case 0x2000:  in sun50i_h616_efuse_xlate()
89 		value = 0;  in sun50i_h616_efuse_xlate()
91 	case 0x2400:  in sun50i_h616_efuse_xlate()
92 	case 0x7400:  in sun50i_h616_efuse_xlate()
93 	case 0x2c00:  in sun50i_h616_efuse_xlate()
94 	case 0x7c00:  in sun50i_h616_efuse_xlate()
103 	case 0x5000:  in sun50i_h616_efuse_xlate()
104 	case 0x5400:  in sun50i_h616_efuse_xlate()
105 	case 0x6000:  in sun50i_h616_efuse_xlate()
108 	case 0x5c00:  in sun50i_h616_efuse_xlate()
111 	case 0x5d00:  in sun50i_h616_efuse_xlate()
112 		value = 0;  in sun50i_h616_efuse_xlate()
114 	case 0x6c00:  in sun50i_h616_efuse_xlate()
118 		pr_warn("sun50i-cpufreq-nvmem: unknown speed bin 0x%x, using default bin 0\n",  in sun50i_h616_efuse_xlate()
119 			speedbin & 0xffff);  in sun50i_h616_efuse_xlate()
120 		value = 0;  in sun50i_h616_efuse_xlate()
166 	cpu_dev = get_cpu_device(0);  in dt_has_supported_hw()
200 	cpu_dev = get_cpu_device(0);  in sun50i_cpufreq_get_efuse()
247 	if (speed < 0) {  in sun50i_cpufreq_nvmem_probe()
274 		if (ret < 0)  in sun50i_cpufreq_nvmem_probe()
281 							  NULL, 0);  in sun50i_cpufreq_nvmem_probe()
284 		return 0;  in sun50i_cpufreq_nvmem_probe()
351 	if (unlikely(ret < 0))  in sun50i_cpufreq_init()
356 						-1, NULL, 0);  in sun50i_cpufreq_init()
358 	if (ret == 0)  in sun50i_cpufreq_init()
359 		return 0;  in sun50i_cpufreq_init()