45 #define ME4000_AO_CHAN(x)			((x) * 0x18)
47 #define ME4000_AO_CTRL_REG(x)			(0x00 + ME4000_AO_CHAN(x))
48 #define ME4000_AO_CTRL_MODE_0			BIT(0)
58 #define ME4000_AO_STATUS_REG(x)			(0x04 + ME4000_AO_CHAN(x))
59 #define ME4000_AO_STATUS_FSM			BIT(0)
63 #define ME4000_AO_FIFO_REG(x)			(0x08 + ME4000_AO_CHAN(x))
64 #define ME4000_AO_SINGLE_REG(x)			(0x0c + ME4000_AO_CHAN(x))
65 #define ME4000_AO_TIMER_REG(x)			(0x10 + ME4000_AO_CHAN(x))
66 #define ME4000_AI_CTRL_REG			0x74
67 #define ME4000_AI_STATUS_REG			0x74
68 #define ME4000_AI_CTRL_MODE_0			BIT(0)
99 #define ME4000_AI_CHANNEL_LIST_REG		0x78
103 #define ME4000_AI_DATA_REG			0x7c
104 #define ME4000_AI_CHAN_TIMER_REG		0x80
105 #define ME4000_AI_CHAN_PRE_TIMER_REG		0x84
106 #define ME4000_AI_SCAN_TIMER_LOW_REG		0x88
107 #define ME4000_AI_SCAN_TIMER_HIGH_REG		0x8c
108 #define ME4000_AI_SCAN_PRE_TIMER_LOW_REG	0x90
109 #define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG	0x94
110 #define ME4000_AI_START_REG			0x98
111 #define ME4000_IRQ_STATUS_REG			0x9c
112 #define ME4000_IRQ_STATUS_EX			BIT(0)
120 #define ME4000_DIO_PORT_0_REG			0xa0
121 #define ME4000_DIO_PORT_1_REG			0xa4
122 #define ME4000_DIO_PORT_2_REG			0xa8
123 #define ME4000_DIO_PORT_3_REG			0xac
124 #define ME4000_DIO_DIR_REG			0xb0
125 #define ME4000_AO_LOADSETREG_XX			0xb4
126 #define ME4000_DIO_CTRL_REG			0xb8
127 #define ME4000_DIO_CTRL_MODE_0			BIT(0)
141 #define ME4000_AO_DEMUX_ADJUST_REG		0xbc
142 #define ME4000_AO_DEMUX_ADJUST_VALUE		0x4c
143 #define ME4000_AI_SAMPLE_COUNTER_REG		0xc0
333 	inb(xilinx_iobase + 0xC8);  in me4000_xilinx_download()
349 	file_length = (((unsigned int)data[0] & 0xff) << 24) +  in me4000_xilinx_download()
350 		      (((unsigned int)data[1] & 0xff) << 16) +  in me4000_xilinx_download()
351 		      (((unsigned int)data[2] & 0xff) << 8) +  in me4000_xilinx_download()
352 		      ((unsigned int)data[3] & 0xff);  in me4000_xilinx_download()
355 	for (i = 0; i < file_length; i++) {  in me4000_xilinx_download()
381 	return 0;  in me4000_xilinx_download()
394 	outl(0x0, dev->iobase + ME4000_AI_CTRL_REG);  in me4000_ai_reset()
404 	outl(0, devpriv->plx_regbase + PLX9052_INTCSR);  in me4000_reset()
413 	/* 0x8000 to the DACs means an output voltage of 0V */  in me4000_reset()
414 	for (chan = 0; chan < 4; chan++)  in me4000_reset()
415 		outl(0x8000, dev->iobase + ME4000_AO_SINGLE_REG(chan));  in me4000_reset()
421 	for (chan = 0; chan < 4; chan++)  in me4000_reset()
429 	 * Set digital I/O direction for port 0  in me4000_reset()
432 	if (!(inl(dev->iobase + ME4000_DIO_DIR_REG) & 0x1))  in me4000_reset()
433 		outl(0x1, dev->iobase + ME4000_DIO_CTRL_REG);  in me4000_reset()
455 		return 0;  in me4000_ai_eoc()
468 	int ret = 0;  in me4000_ai_insn_read()
506 	for (i = 0; i < insn->n; i++) {  in me4000_ai_insn_read()
512 		ret = comedi_timeout(dev, s, insn, me4000_ai_eoc, 0);  in me4000_ai_insn_read()
530 	return 0;  in me4000_ai_cancel()
537 	unsigned int aref0 = CR_AREF(cmd->chanlist[0]);  in me4000_ai_check_chanlist()
540 	for (i = 0; i < cmd->chanlist_len; i++) {  in me4000_ai_check_chanlist()
572 	return 0;  in me4000_ai_check_chanlist()
582 	devpriv->ai_init_ticks = 0;  in me4000_ai_round_cmd_args()
583 	devpriv->ai_scan_ticks = 0;  in me4000_ai_round_cmd_args()
584 	devpriv->ai_chan_ticks = 0;  in me4000_ai_round_cmd_args()
632 	for (i = 0; i < cmd->chanlist_len; i++) {  in me4000_ai_write_chanlist()
660 	outl(0x0, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_HIGH_REG);  in me4000_ai_do_cmd()
665 		outl(0x0, dev->iobase + ME4000_AI_SCAN_TIMER_HIGH_REG);  in me4000_ai_do_cmd()
700 	return 0;  in me4000_ai_do_cmd()
708 	int err = 0;  in me4000_ai_do_cmd_test()
768 	err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);  in me4000_ai_do_cmd_test()
794 		err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);  in me4000_ai_do_cmd_test()
899 		if (cmd->scan_end_arg == 0) {  in me4000_ai_do_cmd_test()
910 	if (cmd->chanlist && cmd->chanlist_len > 0)  in me4000_ai_do_cmd_test()
916 	return 0;  in me4000_ai_do_cmd_test()
925 	int c = 0;  in me4000_ai_isr()
949 			c = 0;  in me4000_ai_isr()
952 		for (i = 0; i < c; i++) {  in me4000_ai_isr()
1005 	outl(0x0, dev->iobase + ME4000_AO_CTRL_REG(chan));  in me4000_ao_insn_write()
1008 	outl(data[0], dev->iobase + ME4000_AO_SINGLE_REG(chan));  in me4000_ao_insn_write()
1011 	s->readback[chan] = data[0];  in me4000_ao_insn_write()
1022 		outl((s->state >> 0) & 0xFF,  in me4000_dio_insn_bits()
1024 		outl((s->state >> 8) & 0xFF,  in me4000_dio_insn_bits()
1026 		outl((s->state >> 16) & 0xFF,  in me4000_dio_insn_bits()
1028 		outl((s->state >> 24) & 0xFF,  in me4000_dio_insn_bits()
1032 	data[1] = ((inl(dev->iobase + ME4000_DIO_PORT_0_REG) & 0xFF) << 0) |  in me4000_dio_insn_bits()
1033 		  ((inl(dev->iobase + ME4000_DIO_PORT_1_REG) & 0xFF) << 8) |  in me4000_dio_insn_bits()
1034 		  ((inl(dev->iobase + ME4000_DIO_PORT_2_REG) & 0xFF) << 16) |  in me4000_dio_insn_bits()
1035 		  ((inl(dev->iobase + ME4000_DIO_PORT_3_REG) & 0xFF) << 24);  in me4000_dio_insn_bits()
1051 		mask = 0x000000ff;  in me4000_dio_insn_config()
1053 		mask = 0x0000ff00;  in me4000_dio_insn_config()
1055 		mask = 0x00ff0000;  in me4000_dio_insn_config()
1057 		mask = 0xff000000;  in me4000_dio_insn_config()
1068 	if (s->io_bits & 0x000000ff)  in me4000_dio_insn_config()
1070 	if (s->io_bits & 0x0000ff00)  in me4000_dio_insn_config()
1072 	if (s->io_bits & 0x00ff0000)  in me4000_dio_insn_config()
1074 	if (s->io_bits & 0xff000000)  in me4000_dio_insn_config()
1083 		s->io_bits |= 0x000000ff;  in me4000_dio_insn_config()
1084 		s->io_bits &= ~0x0000ff00;  in me4000_dio_insn_config()
1124 				      me4000_xilinx_download, 0);  in me4000_auto_attach()
1125 	if (result < 0)  in me4000_auto_attach()
1130 	if (pcidev->irq > 0) {  in me4000_auto_attach()
1133 		if (result == 0) {  in me4000_auto_attach()
1148 	s = &dev->subdevices[0];  in me4000_auto_attach()
1154 	s->maxdata	= 0xffff;  in me4000_auto_attach()
1173 		s->maxdata	= 0xffff;  in me4000_auto_attach()
1199 		s->io_bits |= 0xFF;  in me4000_auto_attach()
1212 		dev->pacer = comedi_8254_io_alloc(timer_base, 0, I8254_IO8, 0);  in me4000_auto_attach()
1221 	return 0;  in me4000_auto_attach()
1230 		outl(0, devpriv->plx_regbase + PLX9052_INTCSR);  in me4000_detach()
1249 	{ PCI_VDEVICE(MEILHAUS, 0x4650), BOARD_ME4650 },
1250 	{ PCI_VDEVICE(MEILHAUS, 0x4660), BOARD_ME4660 },
1251 	{ PCI_VDEVICE(MEILHAUS, 0x4661), BOARD_ME4660I },
1252 	{ PCI_VDEVICE(MEILHAUS, 0x4662), BOARD_ME4660S },
1253 	{ PCI_VDEVICE(MEILHAUS, 0x4663), BOARD_ME4660IS },
1254 	{ PCI_VDEVICE(MEILHAUS, 0x4670), BOARD_ME4670 },
1255 	{ PCI_VDEVICE(MEILHAUS, 0x4671), BOARD_ME4670I },
1256 	{ PCI_VDEVICE(MEILHAUS, 0x4672), BOARD_ME4670S },
1257 	{ PCI_VDEVICE(MEILHAUS, 0x4673), BOARD_ME4670IS },
1258 	{ PCI_VDEVICE(MEILHAUS, 0x4680), BOARD_ME4680 },
1259 	{ PCI_VDEVICE(MEILHAUS, 0x4681), BOARD_ME4680I },
1260 	{ PCI_VDEVICE(MEILHAUS, 0x4682), BOARD_ME4680S },
1261 	{ PCI_VDEVICE(MEILHAUS, 0x4683), BOARD_ME4680IS },
1262 	{ 0 }