Lines Matching +full:interrupt +full:- +full:counter
1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
8 * COMEDI - Linux Control and Measurement Device Interface
30 * ------------- ------------- -------------
32 * 0 PPI-X PPI-X PPI-X
33 * 1 PPI-Y UNUSED UNUSED
34 * 2 CTR-Z1 PPI-Y UNUSED
35 * 3 CTR-Z2 UNUSED UNUSED
36 * 4 INTERRUPT CTR-Z1 CTR-Z1
37 * 5 CTR-Z2 CTR-Z2
39 * 7 INTERRUPT INTERRUPT
43 * ------------- -------------
45 * 0 PPI-X PPI-X1
46 * 1 PPI-Y PPI-X2
47 * 2 PPI-Z PPI-Y1
48 * 3 INTERRUPT PPI-Y2
49 * 4 CTR-Z1
50 * 5 CTR-Z2
52 * 7 INTERRUPT
57 * Port A - channels 0 to 7
58 * Port B - channels 8 to 15
59 * Port CL - channels 16 to 19
60 * Port CH - channels 20 to 23
64 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
71 * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
75 * counter channel into data[1].
77 * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
78 * specified in data[1] (this is a hardware-specific value). Not
82 * 0. CLK n, the counter channel's dedicated CLK input from the SK1
83 * connector. (N.B. for other values, the counter channel's CLKn
90 * 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
91 * 7. Ext Clock, the counter chip's dedicated Ext Clock input from
92 * the SK1 connector. This pin is shared by all three counter
103 * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
107 * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
108 * specified in data[2] (this is a hardware-specific value). Not
114 * 2. GAT n, the counter channel's dedicated GAT input from the SK1
115 * connector. (N.B. for other values, the counter channel's GATn
117 * 3. /OUT n-2, the inverted output of counter channel n-2 (see note
128 * 6. /GAT n, negated version of the counter channel's dedicated
130 * 7. OUT n-2, the non-inverted output of counter channel n-2
145 * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
150 * 1. Clock source OUT n-1 is the output of the preceding channel on the
151 * same counter subdevice if n > 0, or the output of channel 2 on the
152 * preceding counter subdevice (see note 3) if n = 0.
154 * 2. Gate source /OUT n-2 is the inverted output of channel 0 on the
155 * same counter subdevice if n = 2, or the inverted output of channel n+1
156 * on the preceding counter subdevice (see note 3) if n < 2.
158 * 3. The counter subdevices are connected in a ring, so the highest
159 * counter subdevice precedes the lowest.
161 * The 'TIMER' subdevice is a free-running 32-bit timer subdevice.
163 * The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The
164 * digital inputs come from the interrupt status register. The number of
165 * channels matches the number of interrupt sources. The PC214E does not
166 * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
169 * INTERRUPT SOURCES
172 * ------------- ------------- -------------
174 * 0 PPI-X-C0 PPI-X-C0 PPI-X-C0
175 * 1 PPI-X-C3 PPI-X-C3 PPI-X-C3
176 * 2 PPI-Y-C0 PPI-Y-C0 unused
177 * 3 PPI-Y-C3 PPI-Y-C3 unused
178 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1
179 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1
182 * ------------- -------------
184 * 0 PPI-X-C0 PPI-X1-C0
185 * 1 PPI-X-C3 PPI-X1-C3
186 * 2 PPI-Y-C0 PPI-Y1-C0
187 * 3 PPI-Y-C3 PPI-Y1-C3
188 * 4 PPI-Z-C0 CTR-Z1-OUT1
189 * 5 PPI-Z-C3 CTR-Z2-OUT1
191 * When an interrupt source is enabled in the interrupt source enable
193 * bit to 1 in the interrupt status register.
195 * When the interrupt status register value as a whole (actually, just the
196 * 6 least significant bits) goes from zero to non-zero, the board will
197 * generate an interrupt. The interrupt will remain asserted until the
198 * interrupt status register is cleared to zero. To clear a bit to zero in
199 * the interrupt status register, the corresponding interrupt source must
200 * be disabled in the interrupt source enable register (there is no
201 * separate interrupt clear register).
206 * 'INTERRUPT' subdevice. The channel list selects the interrupt sources
208 * TRIG_NOW). The scan begins a short time after the hardware interrupt
209 * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
210 * scan_begin_arg == 0). The value read from the interrupt status register
216 #include <linux/interrupt.h>
307 * This function does some special set-up for the PCIe boards
316 * The board uses Altera Cyclone IV with PCI-Express hard IP. in dio200_pcie_board_setup()
317 * The FPGA configuration has the PCI-Express Avalon-MM Bridge in dio200_pcie_board_setup()
321 * We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt in dio200_pcie_board_setup()
326 dev_err(dev->class_dev, "error! bad PCI region!\n"); in dio200_pcie_board_setup()
327 return -EINVAL; in dio200_pcie_board_setup()
331 dev_err(dev->class_dev, "error! failed to map registers!\n"); in dio200_pcie_board_setup()
332 return -ENOMEM; in dio200_pcie_board_setup()
352 return -EINVAL; in dio200_pci_auto_attach()
353 dev->board_ptr = board; in dio200_pci_auto_attach()
354 dev->board_name = board->name; in dio200_pci_auto_attach()
356 dev_info(dev->class_dev, "%s: attach pci %s (%s)\n", in dio200_pci_auto_attach()
357 dev->driver->driver_name, pci_name(pci_dev), dev->board_name); in dio200_pci_auto_attach()
363 bar = board->mainbar; in dio200_pci_auto_attach()
365 dev->mmio = pci_ioremap_bar(pci_dev, bar); in dio200_pci_auto_attach()
366 if (!dev->mmio) { in dio200_pci_auto_attach()
367 dev_err(dev->class_dev, in dio200_pci_auto_attach()
369 return -ENOMEM; in dio200_pci_auto_attach()
372 dev->iobase = pci_resource_start(pci_dev, bar); in dio200_pci_auto_attach()
374 dev_err(dev->class_dev, in dio200_pci_auto_attach()
376 return -ENXIO; in dio200_pci_auto_attach()
379 if (board->is_pcie) { in dio200_pci_auto_attach()
385 return amplc_dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED); in dio200_pci_auto_attach()
411 id->driver_data); in dio200_pci_probe()