1 // SPDX-License-Identifier: GPL-2.0-only
60  * 1. Read the upper 32-bit timer counter register
61  * 2. Read the lower 32-bit timer counter register
62  * 3. Read the upper 32-bit timer counter register again. If the value is
63  *  different to the 32-bit upper value read previously, go back to step 2.
64  *  Otherwise the 64-bit timer counter value is correct.
69 	u32 lower;  in _gt_counter_read()  local
75 		lower = readl_relaxed(gt_base + GT_COUNTER0);  in _gt_counter_read()
81 	counter |= lower;  in _gt_counter_read()
94  * 2. Write the lower 32-bit Comparator Value Register.
95  * 3. Write the upper 32-bit Comparator Value Register.
155 	 * the same event in single-shot mode)  in gt_clockevent_interrupt()
157 	 *	Either disable single-shot mode.  in gt_clockevent_interrupt()
168 	evt->event_handler(evt);  in gt_clockevent_interrupt()
177 	clk->name = "arm_global_timer";  in gt_starting_cpu()
178 	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |  in gt_starting_cpu()
180 	clk->set_state_shutdown = gt_clockevent_shutdown;  in gt_starting_cpu()
181 	clk->set_state_periodic = gt_clockevent_set_periodic;  in gt_starting_cpu()
182 	clk->set_state_oneshot = gt_clockevent_shutdown;  in gt_starting_cpu()
183 	clk->set_state_oneshot_stopped = gt_clockevent_shutdown;  in gt_starting_cpu()
184 	clk->set_next_event = gt_clockevent_set_next_event;  in gt_starting_cpu()
185 	clk->cpumask = cpumask_of(cpu);  in gt_starting_cpu()
186 	clk->rating = 300;  in gt_starting_cpu()
187 	clk->irq = gt_ppi;  in gt_starting_cpu()
190 	enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);  in gt_starting_cpu()
198 	disable_percpu_irq(clk->irq);  in gt_dying_cpu()
213 		/* re-enable timer on resume */  in gt_resume()
273 			  CONFIG_ARM_GT_INITIAL_PRESCALER_VAL - 1) |  in gt_clocksource_init()
288 	case PRE_RATE_CHANGE:  in gt_clk_rate_change_cb()
292 		psv = DIV_ROUND_CLOSEST(ndata->new_rate, gt_target_rate);  in gt_clk_rate_change_cb()
294 		    abs(gt_target_rate - (ndata->new_rate / psv)) > MAX_F_ERR)  in gt_clk_rate_change_cb()
297 		psv--;  in gt_clk_rate_change_cb()
304 		 * store timer clock ctrl register so we can restore it in case  in gt_clk_rate_change_cb()
309 		/* scale down: adjust divider in post-change notification */  in gt_clk_rate_change_cb()
310 		if (ndata->new_rate < ndata->old_rate)  in gt_clk_rate_change_cb()
313 		/* scale up: adjust divider now - before frequency change */  in gt_clk_rate_change_cb()
317 	case POST_RATE_CHANGE:  in gt_clk_rate_change_cb()
318 		/* scale up: pre-change notification did the adjustment */  in gt_clk_rate_change_cb()
319 		if (ndata->new_rate > ndata->old_rate)  in gt_clk_rate_change_cb()
322 		/* scale down: adjust divider now - after frequency change */  in gt_clk_rate_change_cb()
326 	case ABORT_RATE_CHANGE:  in gt_clk_rate_change_cb()
327 		/* we have to undo the adjustment in case we scale up */  in gt_clk_rate_change_cb()
328 		if (ndata->new_rate < ndata->old_rate)  in gt_clk_rate_change_cb()
354 		pr_warn("global-timer: non support for this cpu version.\n");  in global_timer_of_register()
355 		return -ENOSYS;  in global_timer_of_register()
360 		pr_warn("global-timer: unable to parse irq\n");  in global_timer_of_register()
361 		return -EINVAL;  in global_timer_of_register()
366 		pr_warn("global-timer: invalid base address\n");  in global_timer_of_register()
367 		return -ENXIO;  in global_timer_of_register()
376 		pr_warn("global-timer: clk not found\n");  in global_timer_of_register()
377 		err = -EINVAL;  in global_timer_of_register()
393 		pr_warn("global-timer: can't allocate memory\n");  in global_timer_of_register()
394 		err = -ENOMEM;  in global_timer_of_register()
401 		pr_warn("global-timer: can't register interrupt %d (%d)\n",  in global_timer_of_register()
437 TIMER_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",