Lines Matching +full:only +full:- +full:1 +full:- +full:8 +full:v
1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk-provider.h>
17 #define FAPLL_MAIN_DIV_P_SHIFT 8
50 #define SYNTH_LDMDIV1 BIT(8)
55 #define SYNTH_PHASE_K 8
81 u32 v = readl_relaxed(fd->base); in ti_fapll_clock_is_bypass() local
83 if (fd->bypass_bit_inverted) in ti_fapll_clock_is_bypass()
84 return !(v & FAPLL_MAIN_BP); in ti_fapll_clock_is_bypass()
86 return !!(v & FAPLL_MAIN_BP); in ti_fapll_clock_is_bypass()
91 u32 v = readl_relaxed(fd->base); in ti_fapll_set_bypass() local
93 if (fd->bypass_bit_inverted) in ti_fapll_set_bypass()
94 v &= ~FAPLL_MAIN_BP; in ti_fapll_set_bypass()
96 v |= FAPLL_MAIN_BP; in ti_fapll_set_bypass()
97 writel_relaxed(v, fd->base); in ti_fapll_set_bypass()
102 u32 v = readl_relaxed(fd->base); in ti_fapll_clear_bypass() local
104 if (fd->bypass_bit_inverted) in ti_fapll_clear_bypass()
105 v |= FAPLL_MAIN_BP; in ti_fapll_clear_bypass()
107 v &= ~FAPLL_MAIN_BP; in ti_fapll_clear_bypass()
108 writel_relaxed(v, fd->base); in ti_fapll_clear_bypass()
114 u32 v; in ti_fapll_wait_lock() local
116 while ((v = readl_relaxed(fd->base))) { in ti_fapll_wait_lock()
117 if (v & FAPLL_MAIN_LOCK) in ti_fapll_wait_lock()
120 if (retries-- <= 0) in ti_fapll_wait_lock()
123 udelay(1); in ti_fapll_wait_lock()
126 pr_err("%s failed to lock\n", fd->name); in ti_fapll_wait_lock()
128 return -ETIMEDOUT; in ti_fapll_wait_lock()
134 u32 v = readl_relaxed(fd->base); in ti_fapll_enable() local
136 v |= FAPLL_MAIN_PLLEN; in ti_fapll_enable()
137 writel_relaxed(v, fd->base); in ti_fapll_enable()
146 u32 v = readl_relaxed(fd->base); in ti_fapll_disable() local
148 v &= ~FAPLL_MAIN_PLLEN; in ti_fapll_disable()
149 writel_relaxed(v, fd->base); in ti_fapll_disable()
155 u32 v = readl_relaxed(fd->base); in ti_fapll_is_enabled() local
157 return v & FAPLL_MAIN_PLLEN; in ti_fapll_is_enabled()
164 u32 fapll_n, fapll_p, v; in ti_fapll_recalc_rate() local
172 /* PLL pre-divider is P and multiplier is N */ in ti_fapll_recalc_rate()
173 v = readl_relaxed(fd->base); in ti_fapll_recalc_rate()
174 fapll_p = (v >> 8) & 0xff; in ti_fapll_recalc_rate()
177 fapll_n = v >> 16; in ti_fapll_recalc_rate()
189 return 1; in ti_fapll_get_parent()
201 * right. It seems the divider can only be used together in ti_fapll_set_div_mult()
206 return -EINVAL; in ti_fapll_set_div_mult()
211 return -EINVAL; in ti_fapll_set_div_mult()
212 *pre_div_p = 1; in ti_fapll_set_div_mult()
224 return -EINVAL; in ti_fapll_round_rate()
241 u32 pre_div_p, mult_n, v; in ti_fapll_set_rate() local
245 return -EINVAL; in ti_fapll_set_rate()
253 v = readl_relaxed(fd->base); in ti_fapll_set_rate()
254 v &= ~FAPLL_MAIN_CLEAR_MASK; in ti_fapll_set_rate()
255 v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT; in ti_fapll_set_rate()
256 v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT; in ti_fapll_set_rate()
257 writel_relaxed(v, fd->base); in ti_fapll_set_rate()
278 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); in ti_fapll_synth_enable() local
280 v &= ~(1 << synth->index); in ti_fapll_synth_enable()
281 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); in ti_fapll_synth_enable()
289 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); in ti_fapll_synth_disable() local
291 v |= 1 << synth->index; in ti_fapll_synth_disable()
292 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); in ti_fapll_synth_disable()
298 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); in ti_fapll_synth_is_enabled() local
300 return !(v & (1 << synth->index)); in ti_fapll_synth_is_enabled()
314 if (!synth->div) in ti_fapll_synth_recalc_rate()
322 if (ti_fapll_clock_is_bypass(synth->fd)) in ti_fapll_synth_recalc_rate()
329 * Note that the phase output K is 8, so the result needs in ti_fapll_synth_recalc_rate()
332 if (synth->freq) { in ti_fapll_synth_recalc_rate()
333 u32 v, synth_int_div, synth_frac_div, synth_div_freq; in ti_fapll_synth_recalc_rate() local
335 v = readl_relaxed(synth->freq); in ti_fapll_synth_recalc_rate()
336 synth_int_div = (v >> 24) & 0xf; in ti_fapll_synth_recalc_rate()
337 synth_frac_div = v & 0xffffff; in ti_fapll_synth_recalc_rate()
344 /* Synth post-divider M */ in ti_fapll_synth_recalc_rate()
345 synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M; in ti_fapll_synth_recalc_rate()
358 post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M; in ti_fapll_synth_get_frac_rate()
368 u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v; in ti_fapll_synth_set_frac_rate() local
373 return -EINVAL; in ti_fapll_synth_set_frac_rate()
375 post_div_m = 1; in ti_fapll_synth_set_frac_rate()
390 return -EINVAL; in ti_fapll_synth_set_frac_rate()
392 v = readl_relaxed(synth->freq); in ti_fapll_synth_set_frac_rate()
393 v &= ~0x1fffffff; in ti_fapll_synth_set_frac_rate()
394 v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24; in ti_fapll_synth_set_frac_rate()
395 v |= (synth_frac_div & 0xffffff); in ti_fapll_synth_set_frac_rate()
396 v |= SYNTH_LDFREQ; in ti_fapll_synth_set_frac_rate()
397 writel_relaxed(v, synth->freq); in ti_fapll_synth_set_frac_rate()
406 struct fapll_data *fd = synth->fd; in ti_fapll_synth_round_rate()
409 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate) in ti_fapll_synth_round_rate()
410 return -EINVAL; in ti_fapll_synth_round_rate()
412 /* Only post divider m available with no fractional divider? */ in ti_fapll_synth_round_rate()
413 if (!synth->freq) { in ti_fapll_synth_round_rate()
440 struct fapll_data *fd = synth->fd; in ti_fapll_synth_set_rate()
442 u32 post_div_m = 0, v; in ti_fapll_synth_set_rate() local
444 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate) in ti_fapll_synth_set_rate()
445 return -EINVAL; in ti_fapll_synth_set_rate()
450 if (!synth->freq) in ti_fapll_synth_set_rate()
451 return -EINVAL; in ti_fapll_synth_set_rate()
456 if (!synth->freq && !post_rate) in ti_fapll_synth_set_rate()
457 return -EINVAL; in ti_fapll_synth_set_rate()
461 if ((post_rate != rate) && synth->freq) in ti_fapll_synth_set_rate()
466 v = readl_relaxed(synth->div); in ti_fapll_synth_set_rate()
467 v &= ~SYNTH_MAX_DIV_M; in ti_fapll_synth_set_rate()
468 v |= post_div_m; in ti_fapll_synth_set_rate()
469 v |= SYNTH_LDMDIV1; in ti_fapll_synth_set_rate()
470 writel_relaxed(v, synth->div); in ti_fapll_synth_set_rate()
494 struct clk *clk = ERR_PTR(-ENOMEM); in ti_fapll_synth_setup()
498 return ERR_PTR(-ENOMEM); in ti_fapll_synth_setup()
500 init->ops = &ti_fapll_synt_ops; in ti_fapll_synth_setup()
501 init->name = name; in ti_fapll_synth_setup()
502 init->parent_names = &parent; in ti_fapll_synth_setup()
503 init->num_parents = 1; in ti_fapll_synth_setup()
509 synth->fd = fd; in ti_fapll_synth_setup()
510 synth->index = index; in ti_fapll_synth_setup()
511 synth->freq = freq; in ti_fapll_synth_setup()
512 synth->div = div; in ti_fapll_synth_setup()
513 synth->name = name; in ti_fapll_synth_setup()
514 synth->hw.init = init; in ti_fapll_synth_setup()
515 synth->clk_pll = pll_clk; in ti_fapll_synth_setup()
517 clk = clk_register(NULL, &synth->hw); in ti_fapll_synth_setup()
545 fd->outputs.clks = kzalloc(sizeof(struct clk *) * in ti_fapll_setup()
546 MAX_FAPLL_OUTPUTS + 1, in ti_fapll_setup()
548 if (!fd->outputs.clks) in ti_fapll_setup()
555 init->ops = &ti_fapll_ops; in ti_fapll_setup()
557 init->name = name; in ti_fapll_setup()
559 init->num_parents = of_clk_get_parent_count(node); in ti_fapll_setup()
560 if (init->num_parents != 2) { in ti_fapll_setup()
566 init->parent_names = parent_name; in ti_fapll_setup()
568 fd->clk_ref = of_clk_get(node, 0); in ti_fapll_setup()
569 if (IS_ERR(fd->clk_ref)) { in ti_fapll_setup()
574 fd->clk_bypass = of_clk_get(node, 1); in ti_fapll_setup()
575 if (IS_ERR(fd->clk_bypass)) { in ti_fapll_setup()
580 fd->base = of_iomap(node, 0); in ti_fapll_setup()
581 if (!fd->base) { in ti_fapll_setup()
586 if (fapll_is_ddr_pll(fd->base)) in ti_fapll_setup()
587 fd->bypass_bit_inverted = true; in ti_fapll_setup()
589 fd->name = name; in ti_fapll_setup()
590 fd->hw.init = init; in ti_fapll_setup()
593 pll_clk = clk_register(NULL, &fd->hw); in ti_fapll_setup()
597 fd->outputs.clks[0] = pll_clk; in ti_fapll_setup()
598 fd->outputs.clk_num++; in ti_fapll_setup()
601 * Set up the child synthesizers starting at index 1 as the in ti_fapll_setup()
602 * PLL output is at index 0. We need to check the clock-indices in ti_fapll_setup()
612 u32 v; in ti_fapll_setup() local
614 if (of_property_read_string_index(node, "clock-output-names", in ti_fapll_setup()
618 if (of_property_read_u32_index(node, "clock-indices", i, in ti_fapll_setup()
622 freq = fd->base + (output_instance * 8); in ti_fapll_setup()
631 v = readl_relaxed(freq); in ti_fapll_setup()
632 if (!v) in ti_fapll_setup()
640 fd->outputs.clks[output_instance] = synth_clk; in ti_fapll_setup()
641 fd->outputs.clk_num++; in ti_fapll_setup()
647 of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs); in ti_fapll_setup()
655 iounmap(fd->base); in ti_fapll_setup()
657 if (fd->clk_bypass) in ti_fapll_setup()
658 clk_put(fd->clk_bypass); in ti_fapll_setup()
659 if (fd->clk_ref) in ti_fapll_setup()
660 clk_put(fd->clk_ref); in ti_fapll_setup()
661 kfree(fd->outputs.clks); in ti_fapll_setup()
666 CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup);