1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/clk.h>
4 #include <linux/clk-provider.h>
11 #include <linux/clk/ti.h>
49 /* Synthesizer divider register */
63 	struct clk *clk_ref;
64 	struct clk *clk_bypass;
76 	struct clk *clk_pll;
81 	u32 v = readl_relaxed(fd->base);  in ti_fapll_clock_is_bypass()
83 	if (fd->bypass_bit_inverted)  in ti_fapll_clock_is_bypass()
91 	u32 v = readl_relaxed(fd->base);  in ti_fapll_set_bypass()
93 	if (fd->bypass_bit_inverted)  in ti_fapll_set_bypass()
97 	writel_relaxed(v, fd->base);  in ti_fapll_set_bypass()
102 	u32 v = readl_relaxed(fd->base);  in ti_fapll_clear_bypass()
104 	if (fd->bypass_bit_inverted)  in ti_fapll_clear_bypass()
108 	writel_relaxed(v, fd->base);  in ti_fapll_clear_bypass()
116 	while ((v = readl_relaxed(fd->base))) {  in ti_fapll_wait_lock()
120 		if (retries-- <= 0)  in ti_fapll_wait_lock()
126 	pr_err("%s failed to lock\n", fd->name);  in ti_fapll_wait_lock()
128 	return -ETIMEDOUT;  in ti_fapll_wait_lock()
134 	u32 v = readl_relaxed(fd->base);  in ti_fapll_enable()
137 	writel_relaxed(v, fd->base);  in ti_fapll_enable()
146 	u32 v = readl_relaxed(fd->base);  in ti_fapll_disable()
149 	writel_relaxed(v, fd->base);  in ti_fapll_disable()
155 	u32 v = readl_relaxed(fd->base);  in ti_fapll_is_enabled()
172 	/* PLL pre-divider is P and multiplier is N */  in ti_fapll_recalc_rate()
173 	v = readl_relaxed(fd->base);  in ti_fapll_recalc_rate()
199 	 * So far no luck getting decent clock with PLL divider,  in ti_fapll_set_div_mult()
201 	 * right. It seems the divider can only be used together  in ti_fapll_set_div_mult()
205 		pr_warn("FAPLL main divider rates unsupported\n");  in ti_fapll_set_div_mult()
206 		return -EINVAL;  in ti_fapll_set_div_mult()
211 		return -EINVAL;  in ti_fapll_set_div_mult()
224 		return -EINVAL;  in ti_fapll_round_rate()
245 		return -EINVAL;  in ti_fapll_set_rate()
253 	v = readl_relaxed(fd->base);  in ti_fapll_set_rate()
257 	writel_relaxed(v, fd->base);  in ti_fapll_set_rate()
278 	u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);  in ti_fapll_synth_enable()
280 	v &= ~(1 << synth->index);  in ti_fapll_synth_enable()
281 	writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);  in ti_fapll_synth_enable()
289 	u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);  in ti_fapll_synth_disable()
291 	v |= 1 << synth->index;  in ti_fapll_synth_disable()
292 	writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);  in ti_fapll_synth_disable()
298 	u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);  in ti_fapll_synth_is_enabled()
300 	return !(v & (1 << synth->index));  in ti_fapll_synth_is_enabled()
314 	if (!synth->div)  in ti_fapll_synth_recalc_rate()
318 	 * PLL in bypass sets the synths in bypass mode too. The PLL rate  in ti_fapll_synth_recalc_rate()
320 	 * check for bypass mode.  in ti_fapll_synth_recalc_rate()
322 	if (ti_fapll_clock_is_bypass(synth->fd))  in ti_fapll_synth_recalc_rate()
328 	 * Synth frequency integer and fractional divider.  in ti_fapll_synth_recalc_rate()
332 	if (synth->freq) {  in ti_fapll_synth_recalc_rate()
335 		v = readl_relaxed(synth->freq);  in ti_fapll_synth_recalc_rate()
344 	/* Synth post-divider M */  in ti_fapll_synth_recalc_rate()
345 	synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;  in ti_fapll_synth_recalc_rate()
358 	post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;  in ti_fapll_synth_get_frac_rate()
373 		return -EINVAL;  in ti_fapll_synth_set_frac_rate()
390 		return -EINVAL;  in ti_fapll_synth_set_frac_rate()
392 	v = readl_relaxed(synth->freq);  in ti_fapll_synth_set_frac_rate()
397 	writel_relaxed(v, synth->freq);  in ti_fapll_synth_set_frac_rate()
406 	struct fapll_data *fd = synth->fd;  in ti_fapll_synth_round_rate()
409 	if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)  in ti_fapll_synth_round_rate()
410 		return -EINVAL;  in ti_fapll_synth_round_rate()
412 	/* Only post divider m available with no fractional divider? */  in ti_fapll_synth_round_rate()
413 	if (!synth->freq) {  in ti_fapll_synth_round_rate()
440 	struct fapll_data *fd = synth->fd;  in ti_fapll_synth_set_rate()
444 	if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)  in ti_fapll_synth_set_rate()
445 		return -EINVAL;  in ti_fapll_synth_set_rate()
447 	/* Produce the rate with just post divider M? */  in ti_fapll_synth_set_rate()
450 		if (!synth->freq)  in ti_fapll_synth_set_rate()
451 			return -EINVAL;  in ti_fapll_synth_set_rate()
456 		if (!synth->freq && !post_rate)  in ti_fapll_synth_set_rate()
457 			return -EINVAL;  in ti_fapll_synth_set_rate()
460 	/* Need to recalculate the fractional divider? */  in ti_fapll_synth_set_rate()
461 	if ((post_rate != rate) && synth->freq)  in ti_fapll_synth_set_rate()
466 	v = readl_relaxed(synth->div);  in ti_fapll_synth_set_rate()
470 	writel_relaxed(v, synth->div);  in ti_fapll_synth_set_rate()
484 static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,  in ti_fapll_synth_setup()
490 						struct clk *pll_clk)  in ti_fapll_synth_setup()
494 	struct clk *clk = ERR_PTR(-ENOMEM);  in ti_fapll_synth_setup()  local
498 		return ERR_PTR(-ENOMEM);  in ti_fapll_synth_setup()
500 	init->ops = &ti_fapll_synt_ops;  in ti_fapll_synth_setup()
501 	init->name = name;  in ti_fapll_synth_setup()
502 	init->parent_names = &parent;  in ti_fapll_synth_setup()
503 	init->num_parents = 1;  in ti_fapll_synth_setup()
509 	synth->fd = fd;  in ti_fapll_synth_setup()
510 	synth->index = index;  in ti_fapll_synth_setup()
511 	synth->freq = freq;  in ti_fapll_synth_setup()
512 	synth->div = div;  in ti_fapll_synth_setup()
513 	synth->name = name;  in ti_fapll_synth_setup()
514 	synth->hw.init = init;  in ti_fapll_synth_setup()
515 	synth->clk_pll = pll_clk;  in ti_fapll_synth_setup()
517 	clk = clk_register(NULL, &synth->hw);  in ti_fapll_synth_setup()
518 	if (IS_ERR(clk)) {  in ti_fapll_synth_setup()
523 	return clk;  in ti_fapll_synth_setup()
529 	return clk;  in ti_fapll_synth_setup()
537 	struct clk *pll_clk;  in ti_fapll_setup()
545 	fd->outputs.clks = kzalloc(sizeof(struct clk *) *  in ti_fapll_setup()
548 	if (!fd->outputs.clks)  in ti_fapll_setup()
555 	init->ops = &ti_fapll_ops;  in ti_fapll_setup()
557 	init->name = name;  in ti_fapll_setup()
559 	init->num_parents = of_clk_get_parent_count(node);  in ti_fapll_setup()
560 	if (init->num_parents != 2) {  in ti_fapll_setup()
566 	init->parent_names = parent_name;  in ti_fapll_setup()
568 	fd->clk_ref = of_clk_get(node, 0);  in ti_fapll_setup()
569 	if (IS_ERR(fd->clk_ref)) {  in ti_fapll_setup()
574 	fd->clk_bypass = of_clk_get(node, 1);  in ti_fapll_setup()
575 	if (IS_ERR(fd->clk_bypass)) {  in ti_fapll_setup()
580 	fd->base = of_iomap(node, 0);  in ti_fapll_setup()
581 	if (!fd->base) {  in ti_fapll_setup()
586 	if (fapll_is_ddr_pll(fd->base))  in ti_fapll_setup()
587 		fd->bypass_bit_inverted = true;  in ti_fapll_setup()
589 	fd->name = name;  in ti_fapll_setup()
590 	fd->hw.init = init;  in ti_fapll_setup()
593 	pll_clk = clk_register(NULL, &fd->hw);  in ti_fapll_setup()
597 	fd->outputs.clks[0] = pll_clk;  in ti_fapll_setup()
598 	fd->outputs.clk_num++;  in ti_fapll_setup()
602 	 * PLL output is at index 0. We need to check the clock-indices  in ti_fapll_setup()
610 		struct clk *synth_clk;  in ti_fapll_setup()
614 		if (of_property_read_string_index(node, "clock-output-names",  in ti_fapll_setup()
618 		if (of_property_read_u32_index(node, "clock-indices", i,  in ti_fapll_setup()
622 		freq = fd->base + (output_instance * 8);  in ti_fapll_setup()
640 		fd->outputs.clks[output_instance] = synth_clk;  in ti_fapll_setup()
641 		fd->outputs.clk_num++;  in ti_fapll_setup()
647 	of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs);  in ti_fapll_setup()
655 	iounmap(fd->base);  in ti_fapll_setup()
657 	if (fd->clk_bypass)  in ti_fapll_setup()
658 		clk_put(fd->clk_bypass);  in ti_fapll_setup()
659 	if (fd->clk_ref)  in ti_fapll_setup()
660 		clk_put(fd->clk_ref);  in ti_fapll_setup()
661 	kfree(fd->outputs.clks);  in ti_fapll_setup()
666 CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup);