Lines Matching full:24
39 { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
44 …1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:0000:24" },
76 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
98 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
103 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
108 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
113 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
124 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
130 { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
131 { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
132 { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
133 { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
135 { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
156 { 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
215 "atl-clkctrl:0000:24",
220 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
322 { 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },
328 { DRA7_GPU_CLKCTRL, dra7_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24", },
339 "l3init-clkctrl:0008:24",
350 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
356 "l3init-clkctrl:0010:24",
367 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
456 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
482 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
487 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
492 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
497 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
502 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
507 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
547 "l4per-clkctrl:00f8:24",
558 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
564 "l4per-clkctrl:0100:24",
575 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
581 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
586 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
591 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
596 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
601 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
606 { DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" },
607 { DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
608 { DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
609 { DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
610 { DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
611 { DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
632 { DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" },
633 { DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" },
634 { DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" },
635 { DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" },
636 { DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" },
657 "l4per2-clkctrl:012c:24",
667 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
674 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
681 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
687 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
693 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
699 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
704 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
709 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
714 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
720 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
726 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
743 { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
744 { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
745 { DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" },
753 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
758 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
763 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
768 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
774 { DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" },
775 { DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" },
776 { DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" },
777 { DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" },
787 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
792 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
803 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
811 { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
814 { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
815 { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
855 DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
857 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
873 DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
875 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
878 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
880 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
882 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
884 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
886 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
888 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
890 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
894 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
897 DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
900 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
903 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
911 DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
912 DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
914 DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
915 DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
916 DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
917 DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
918 DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
919 DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
920 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
921 DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
922 DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
923 DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
924 DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
925 DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
926 DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
927 DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
928 DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
929 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
930 DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
931 DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
932 DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
933 DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
934 DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
935 DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
936 DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
937 DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
938 DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),