Lines Matching full:24
48 { 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data },
67 { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
80 { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
93 { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
106 { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
118 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
123 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
128 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
133 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
139 { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
141 { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
142 { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
143 { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
144 { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
145 { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
146 { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
147 { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
148 { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
201 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
206 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
211 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
216 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
221 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
226 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
271 { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
272 { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
273 { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
274 { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
275 { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
276 { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0030:24" },
374 { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
381 { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24" },
392 "l3init-clkctrl:0008:24",
402 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
408 "l3init-clkctrl:0010:24",
417 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
433 "l3init-clkctrl:0038:24",
464 { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
514 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
522 { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
552 DT_CLK(NULL, "dmic_gfclk", "abe-clkctrl:0018:24"),
566 DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"),
569 DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"),
572 DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"),
577 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
579 DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
582 DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"),
583 DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"),
584 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
585 DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0018:24"),
586 DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0020:24"),
587 DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0028:24"),
588 DT_CLK(NULL, "timer5_gfclk_mux", "abe-clkctrl:0048:24"),
589 DT_CLK(NULL, "timer6_gfclk_mux", "abe-clkctrl:0050:24"),
590 DT_CLK(NULL, "timer7_gfclk_mux", "abe-clkctrl:0058:24"),
591 DT_CLK(NULL, "timer8_gfclk_mux", "abe-clkctrl:0060:24"),
592 DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0030:24"),
606 DT_CLK(NULL, "utmi_p1_gfclk", "l3init-clkctrl:0038:24"),