Lines Matching full:24
54 { 24, TI_CLK_DIVIDER, omap4_aess_fclk_parents, &omap4_aess_fclk_data },
73 { 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL },
86 { 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL },
99 { 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL },
112 { 24, TI_CLK_MUX, omap4_func_mcbsp2_gfclk_parents, NULL },
125 { 24, TI_CLK_MUX, omap4_func_mcbsp3_gfclk_parents, NULL },
165 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
170 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
175 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
180 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
186 { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
188 { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
189 { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" },
190 { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
191 { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
192 { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
194 { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
195 { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
196 { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
197 { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
284 { 24, TI_CLK_DIVIDER, omap4_fdif_fck_parents, &omap4_fdif_fck_data },
290 { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss-clkctrl:0008:24" },
334 { 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL },
339 { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3-gfx-clkctrl:0000:24" },
350 { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
355 { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
370 { 24, TI_CLK_DIVIDER, omap4_hsi_fck_parents, &omap4_hsi_fck_data },
375 "l3-init-clkctrl:0038:24",
415 { 24, TI_CLK_MUX, omap4_utmi_p1_gfclk_parents, NULL },
421 "l3-init-clkctrl:0040:24",
433 { 24, TI_CLK_MUX, omap4_otg_60m_gfclk_parents, NULL },
455 { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0008:24" },
456 { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0010:24" },
457 { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:0018:24" },
473 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
478 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
483 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
488 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
493 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
498 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
545 { 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
573 { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0008:24" },
574 { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0010:24" },
575 { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0018:24" },
576 { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0020:24" },
577 { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0028:24" },
578 { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0030:24" },
591 { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:00c0:24" },
625 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
633 { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4-wkup-clkctrl:0020:24" },
677 { 24, TI_CLK_DIVIDER, omap4_trace_clk_div_div_ck_parents, &omap4_trace_clk_div_div_ck_data },
719 DT_CLK(NULL, "aess_fclk", "abe-clkctrl:0008:24"),
720 DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"),
721 DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"),
722 DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"),
723 DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"),
724 DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"),
725 DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"),
727 DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"),
732 DT_CLK(NULL, "fdif_fck", "iss-clkctrl:0008:24"),
733 DT_CLK(NULL, "func_dmic_abe_gfclk", "abe-clkctrl:0018:24"),
734 DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe-clkctrl:0020:24"),
735 DT_CLK(NULL, "func_mcbsp1_gfclk", "abe-clkctrl:0028:24"),
736 DT_CLK(NULL, "func_mcbsp2_gfclk", "abe-clkctrl:0030:24"),
737 DT_CLK(NULL, "func_mcbsp3_gfclk", "abe-clkctrl:0038:24"),
744 DT_CLK(NULL, "hsi_fck", "l3-init-clkctrl:0018:24"),
745 DT_CLK(NULL, "hsmmc1_fclk", "l3-init-clkctrl:0008:24"),
746 DT_CLK(NULL, "hsmmc2_fclk", "l3-init-clkctrl:0010:24"),
758 DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"),
760 DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
763 DT_CLK(NULL, "sgx_clk_mux", "l3-gfx-clkctrl:0000:24"),
772 DT_CLK(NULL, "timer5_sync_mux", "abe-clkctrl:0048:24"),
773 DT_CLK(NULL, "timer6_sync_mux", "abe-clkctrl:0050:24"),
774 DT_CLK(NULL, "timer7_sync_mux", "abe-clkctrl:0058:24"),
775 DT_CLK(NULL, "timer8_sync_mux", "abe-clkctrl:0060:24"),
776 DT_CLK(NULL, "trace_clk_div_div_ck", "emu-sys-clkctrl:0000:24"),
789 DT_CLK(NULL, "utmi_p1_gfclk", "l3-init-clkctrl:0038:24"),