Lines Matching +full:12 +full:bit +full:- +full:clk +full:- +full:divider
1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
20 #define CLK_ENB_PLLP_OUT_CPU BIT(31)
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
91 struct clk *tegra_clk_register_sync_source(const char *name,
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
98 * @reg: register containing divider
99 * @flags: hardware-specific flags
100 * @shift: shift to the divider bit field
101 * @width: width of the divider bit field
102 * @frac_width: width of the fractional bit field
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
108 * flag indicates that this divider is for fixed rate PLL.
109 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
110 * fraction bit is set. This flags indicates to calculate divider for which
111 * fracton bit will be zero.
112 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
113 * set when divider value is not 0. This flags indicates that the divider
128 #define TEGRA_DIVIDER_ROUND_UP BIT(0)
129 #define TEGRA_DIVIDER_FIXED BIT(1)
130 #define TEGRA_DIVIDER_INT BIT(2)
131 #define TEGRA_DIVIDER_UART BIT(3)
134 struct clk *tegra_clk_register_divider(const char *name,
138 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
154 * struct tegra_clk_pll_freq_table - PLL frequecy table
158 * @n: feedback divider
159 * @m: input divider
160 * @p: post divider
162 * @sdm_data: fraction divider setting (0 = disabled)
175 * struct pdiv_map - map post divider to hw value
177 * @pdiv: post divider
186 * struct div_nmp - offset and width of m,n and p fields
188 * @divn_shift: shift to the feedback divider bit field
189 * @divn_width: width of the feedback divider bit field
190 * @divm_shift: shift to the input divider bit field
191 * @divm_width: width of the input divider bit field
192 * @divp_shift: shift to the post divider bit field
193 * @divp_width: width of the post divider bit field
194 * @override_divn_shift: shift to the feedback divider bitfield in override reg
195 * @override_divm_shift: shift to the input divider bitfield in override reg
196 * @override_divp_shift: shift to the post divider bitfield in override reg
215 * struct tegra_clk_pll_params - PLL parameters
227 * @lock_enable_bit_idx: Bit index to enable PLL lock
229 * @iddq_bit_idx: Bit index to enable PLL IDDQ
230 * @reset_reg: Register offset of where RESET bit is
231 * @reset_bit_idx: Shift of reset bit in reset_reg
233 * @sdm_din_mask: Mask of SDM divider bits
235 * @sdm_ctrl_en_mask: Mask of SDM enable bit
237 * @ssc_ctrl_en_mask: Mask of SSC enable bit
241 * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM)
242 * @pmc_divp_reg: p divider PMC override register offset (PLLM)
247 * @max_p: maximum value for the p divider
249 * @pdiv_tohw: mapping of p divider to register values
256 * PLL's based on fractional divider value.
260 * divider range (if SDM is present)
275 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
277 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
279 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
281 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
283 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
284 * that it is PLLU and invert post divider value.
285 * TEGRA_PLLM - PLLM has additional override settings in PMC. This
287 * TEGRA_PLL_FIXED - We are not supposed to change output frequency
289 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
290 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
292 * TEGRA_PLL_BYPASS - PLL has bypass bit
293 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
294 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
296 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
298 * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
353 #define TEGRA_PLL_USE_LOCK BIT(0)
354 #define TEGRA_PLL_HAS_CPCON BIT(1)
355 #define TEGRA_PLL_SET_LFCON BIT(2)
356 #define TEGRA_PLL_SET_DCCON BIT(3)
357 #define TEGRA_PLLU BIT(4)
358 #define TEGRA_PLLM BIT(5)
359 #define TEGRA_PLL_FIXED BIT(6)
360 #define TEGRA_PLLE_CONFIGURE BIT(7)
361 #define TEGRA_PLL_LOCK_MISC BIT(8)
362 #define TEGRA_PLL_BYPASS BIT(9)
363 #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
364 #define TEGRA_MDIV_NEW BIT(11)
365 #define TEGRA_PLLMB BIT(12)
366 #define TEGRA_PLL_VCO_OUT BIT(13)
369 * struct tegra_clk_pll - Tegra PLL clock
371 * @hw: handle between common and hardware-specifix interfaces
388 * struct tegra_audio_clk_info - Tegra Audio Clk Information
404 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
409 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
414 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
420 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
426 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
432 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
438 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
444 struct clk *tegra_clk_register_plle_tegra114(const char *name,
450 struct clk *tegra_clk_register_plle_tegra210(const char *name,
456 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
462 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
468 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
473 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
479 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
484 struct clk *tegra_clk_register_pllu_tegra114(const char *name,
490 struct clk *tegra_clk_register_pllu_tegra210(const char *name,
497 * struct tegra_clk_pll_out - PLL divider down clock
499 * @hw: handle between common and hardware-specific interfaces
500 * @reg: register containing the PLL divider
501 * @enb_bit_idx: bit to enable/disable PLL divider
502 * @rst_bit_idx: bit to reset PLL divider
504 * @flags: hardware-specific flags
518 struct clk *tegra_clk_register_pll_out(const char *name,
524 * struct tegra_clk_periph_regs - Registers controlling peripheral clock
543 * struct tegra_clk_periph_gate - peripheral gate clock
546 * @hw: handle between common and hardware-specific interfaces
549 * @flags: hardware-specific flags
554 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
556 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
559 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
576 #define TEGRA_PERIPH_NO_RESET BIT(0)
577 #define TEGRA_PERIPH_ON_APB BIT(2)
578 #define TEGRA_PERIPH_WAR_1005168 BIT(3)
579 #define TEGRA_PERIPH_NO_DIV BIT(4)
580 #define TEGRA_PERIPH_NO_GATE BIT(5)
583 struct clk *tegra_clk_register_periph_gate(const char *name,
596 struct clk *tegra_clk_register_periph_fixed(const char *name,
605 * struct clk-periph - peripheral clock
608 * @hw: handle between common and hardware-specific interfaces
610 * @divider: divider clock
613 * @div_ops: divider clock ops
620 struct tegra_clk_frac_div divider; member
633 struct clk *tegra_clk_register_periph(const char *name,
637 struct clk *tegra_clk_register_periph_nodiv(const char *name,
654 .divider = { \
711 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
716 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
720 * struct clk_super_mux - super clock
722 * @hw: handle between common and hardware-specific interfaces
724 * @width: width of the multiplexer bit field
725 * @flags: hardware-specific flags
726 * @div2_index: bit controlling divide-by-2
731 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
733 * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5
735 * to configure additional bit PLLP_OUT_CPU in the clock registers.
736 * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super
737 * clocks, it only has a clock-skipper.
753 #define TEGRA_DIVIDER_2 BIT(0)
754 #define TEGRA210_CPU_CLK BIT(1)
755 #define TEGRA20_SUPER_CLK BIT(2)
758 struct clk *tegra_clk_register_super_mux(const char *name,
762 struct clk *tegra_clk_register_super_clk(const char *name,
766 struct clk *tegra_clk_register_super_cclk(const char *name,
774 * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
776 * @hw: handle between common and hardware-specific interfaces
777 * @reg: register controlling mux and divider
778 * @flags: hardware-specific flags
794 struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
799 * struct clk_init_table - clock initialization table
813 * struct clk_duplicate - duplicate clocks
846 struct clk *clks[], int clk_max);
849 struct clk *clks[], int clk_max);
852 struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
854 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
881 struct clk *tegra124_clk_register_emc(void __iomem *base, struct device_node *np,
885 static inline struct clk *
925 struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter);
927 struct clk *tegra210_clk_register_emc(struct device_node *np,
930 struct clk *tegra_clk_dev_register(struct clk_hw *hw);