237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)  argument
238 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)  argument
239 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)  argument
240 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)  argument
241 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)  argument
242 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)  argument
278 	u32 val;  in clk_pll_enable_lock()  local
294 	u32 val, lock_mask;  in clk_pll_wait_for_lock()  local
332 	u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);  in pllm_clk_is_gated_by_pmc()  local
341 	u32 val;  in clk_pll_is_enabled()  local
359 	u32 val;  in _clk_pll_enable()  local
392 	u32 val;  in _clk_pll_disable()  local
423 		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);  in pll_clk_start_ss()  local
433 		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);  in pll_clk_stop_ss()  local
631 	u32 val;  in clk_pll_set_sdm_data()  local
658 	u32 val;  in _update_pll_mnp()  local
695 	u32 val;  in _get_pll_mnp()  local
731 	u32 val;  in _update_pll_cpcon()  local
868 	u32 val;  in clk_pll_recalc_rate()  local
916 	u32 val;  in clk_plle_training()  local
960 	u32 val;  in clk_plle_enable()  local
1020 	u32 val = pll_readl_base(pll);  in clk_plle_recalc_rate()  local
1271 	u32 val;  in _setup_dynamic_ramp()  local
1383 	u32 val;  in _pllcx_strobe()  local
1397 	u32 val;  in clk_pllc_enable()  local
1428 	u32 val;  in _clk_pllc_disable()  local
1455 	u32 val, n_threshold;  in _pllcx_update_dynamic_coef()  local
1613 	u32 val;  in clk_plle_tegra114_enable()  local
1724 	u32 val;  in clk_plle_tegra114_disable()  local
1849 	u32 val, val_aux;  in _clk_plle_tegra_init_parent()  local
1871 		spinlock_t *lock)  in _tegra_init_pll()
1923 		spinlock_t *lock)  in tegra_clk_register_pll()
1954 		spinlock_t *lock)  in tegra_clk_register_plle()
1978 		struct tegra_clk_pll_params *pll_params, spinlock_t *lock)  in tegra_clk_register_pllu()
2046 			  spinlock_t *lock)  in tegra_clk_register_pllxc()
2051 	u32 val, val_iddq;  in tegra_clk_register_pllxc()  local
2110 			  spinlock_t *lock, unsigned long parent_rate)  in tegra_clk_register_pllre()
2112 	u32 val;  in tegra_clk_register_pllre()  local
2159 			  spinlock_t *lock)  in tegra_clk_register_pllm()
2201 			  spinlock_t *lock)  in tegra_clk_register_pllc()
2275 				spinlock_t *lock)  in tegra_clk_register_plle_tegra114()
2298 				 spinlock_t *lock)  in tegra_clk_register_pllu_tegra114()
2332 				spinlock_t *lock)  in tegra_clk_register_pllss()
2338 	u32 val, val_iddq;  in tegra_clk_register_pllss()  local
2415 			  spinlock_t *lock, unsigned long parent_rate)  in tegra_clk_register_pllre_tegra210()
2441 	u32 val;  in clk_plle_tegra210_is_enabled()  local
2452 	u32 val;  in clk_plle_tegra210_enable()  local
2531 	u32 val;  in clk_plle_tegra210_disable()  local
2578 				spinlock_t *lock)  in tegra_clk_register_plle_tegra210()
2601 			spinlock_t *lock)  in tegra_clk_register_pllc_tegra210()
2643 				spinlock_t *lock)  in tegra_clk_register_pllss_tegra210()
2648 	u32 val;  in tegra_clk_register_pllss_tegra210()  local
2692 			  spinlock_t *lock)  in tegra_clk_register_pllmb()