Lines Matching +full:24 +full:m
18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
20 * rate = (parent_rate * n >> p) / (m + 1);
21 * parent_rate is always 24MHz
23 * p and m are named div1 and div2 in Allwinner's SDK
29 int m = 1; in sun9i_a80_get_pll4_factors() local
32 /* Normalize value to a 6 MHz multiple (24 MHz / 4) */ in sun9i_a80_get_pll4_factors()
37 m = 0; in sun9i_a80_get_pll4_factors()
41 /* If n is still too large switch to steps of 24 MHz */ in sun9i_a80_get_pll4_factors()
53 req->rate = ((24000000 * n) >> p) / (m + 1); in sun9i_a80_get_pll4_factors()
55 req->m = m; in sun9i_a80_get_pll4_factors()
94 * sun9i_a80_get_gt_factors() - calculates m factor for GT
96 * rate = parent_rate / (m + 1);
113 req->m = div; in sun9i_a80_get_gt_factors()
122 .mux = 24,
177 .mux = 24,
203 .mux = 24,
229 * sun9i_a80_get_apb1_factors() - calculates m, p factors for APB1
231 * rate = (parent_rate >> p) / (m + 1);
243 /* Highest possible divider is 256 (p = 3, m = 31) */ in sun9i_a80_get_apb1_factors()
248 req->m = (req->parent_rate >> req->p) - 1; in sun9i_a80_get_apb1_factors()
249 req->rate = (req->parent_rate >> req->p) / (req->m + 1); in sun9i_a80_get_apb1_factors()
260 .mux = 24,