Lines Matching +full:24 +full:m
33 .m = _SUNXI_CCU_DIV(0, 2),
59 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
60 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
66 0, 5, /* M */
67 pll_audio_sdm_table, BIT(24),
78 0, 4, /* M */
79 BIT(24), /* frac enable */
87 /* TODO: The result of N/M is required to be in [8, 25] range. */
91 0, 4, /* M */
92 BIT(24), /* frac enable */
105 0, 2, /* M */
127 .enable = BIT(24),
130 * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
131 * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
165 0, 4, /* M */
166 BIT(24), /* frac enable */
179 .m = _SUNXI_CCU_DIV(0, 2),
198 /* TODO: The result of N/M is required to be in [8, 25] range. */
202 0, 4, /* M */
203 BIT(24), /* frac enable */
218 * TODO: In the MIPI mode, M/N is required to be equal or lesser than 3,
229 .m = _SUNXI_CCU_DIV(0, 4),
240 /* TODO: The result of N/M is required to be in [8, 25] range. */
244 0, 4, /* M */
245 BIT(24), /* frac enable */
257 0, 2, /* M */
309 0, 5, /* M */
311 24, 2, /* mux */
347 0x060, BIT(24), 0);
396 0x064, BIT(24), 0);
479 .mux = _SUNXI_CCU_MUX(24, 2),
492 0, 4, /* M */
494 24, 2, /* mux */
499 0, 4, /* M */
501 24, 2, /* mux */
506 0, 4, /* M */
508 24, 2, /* mux */
513 0, 4, /* M */
515 24, 2, /* mux */
520 0, 4, /* M */
522 24, 2, /* mux */
528 0, 4, /* M */
530 24, 4, /* mux */
537 0, 4, /* M */
539 24, 2, /* mux */
544 0, 4, /* M */
546 24, 2, /* mux */
551 0, 4, /* M */
553 24, 2, /* mux */
558 0, 4, /* M */
560 24, 2, /* mux */
565 0, 4, /* M */
567 24, 2, /* mux */
592 .m = _SUNXI_CCU_DIV(0, 5),
594 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
606 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
609 * There are 3 OHCI 12M clock source selection bits in this register.
610 * We will force them to 0 (12M divided from 48M).
630 0, 4, /* M */
632 24, 2, /* mux */
637 0, 4, /* M */
639 24, 2, /* mux */
664 0x104, 0, 4, 24, 3, BIT(31),
667 0x108, 0, 4, 24, 3, BIT(31), 0);
673 0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
675 0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
677 0x118, 0, 4, 24, 3, BIT(31),
680 0x11c, 0, 4, 24, 3, BIT(31),
686 deinterlace_parents, 0x124, 0, 4, 24, 3,
696 0x134, 16, 4, 24, 3, BIT(31), 0);
711 0x150, 0, 4, 24, 2, BIT(31),
727 0, 4, /* M */
729 24, 2, /* mux */
739 0x180, 0, 4, 24, 3, BIT(31), 0);
741 0x184, 0, 4, 24, 3, BIT(31), 0);
746 0x188, 0, 4, 24, 3, BIT(31), 0);
748 0x18c, 0, 4, 24, 3, BIT(31), 0);
750 0x190, 0, 4, 24, 3, BIT(31), 0);
752 0x194, 0, 4, 24, 3, BIT(31), 0);
764 .m = _SUNXI_CCU_DIV(8, 5),
767 .shift = 24,
783 .m = _SUNXI_CCU_DIV(8, 5),
786 .shift = 24,
1189 [RST_BUS_SATA] = { 0x2c0, BIT(24) },
1214 [RST_BUS_TVD3] = { 0x2c4, BIT(24) },
1275 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
1276 .bypass_index = 1, /* index of 24 MHz oscillator */
1330 /* Force OHCI 12M parent to 12M divided from 48M */ in sun8i_r40_ccu_probe()