Lines Matching +full:24 +full:m
65 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
74 { .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },
75 { .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 },
82 .m = _SUNXI_CCU_DIV(0, 6),
84 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
102 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
119 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
135 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
151 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
167 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
183 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
199 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
215 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
270 0, 5, /* M */
272 24, 2, /* mux */
320 0x060, BIT(24), 0);
381 .mux = _SUNXI_CCU_MUX(24, 2),
395 0, 4, /* M */
397 24, 2, /* mux */
403 0, 4, /* M */
405 24, 2, /* mux */
416 0, 4, /* M */
418 24, 2, /* mux */
437 0, 4, /* M */
439 24, 2, /* mux */
445 0, 4, /* M */
447 24, 4, /* mux */
453 0, 4, /* M */
455 24, 4, /* mux */
482 .hw.init = CLK_HW_INIT("usb-hsic-12m", "osc24M",
499 0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
503 0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
515 0, 5, /* M */
525 16, 4, /* M */
526 24, 3, /* mux */
538 0, 4, /* M */
539 24, 2, /* mux */
549 0, 3, /* M */
550 24, 2, /* mux */
559 0, 4, /* M */
560 24, 4, /* mux */
569 0, 4, /* M */
570 24, 4, /* mux */
581 0, 3, /* M */
582 24, 1, /* mux */
818 [RST_BUS_OTG] = { 0x2c0, BIT(24) },