Lines Matching +full:24 +full:m
36 0, 2, /* M */
56 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
57 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
63 0, 5, /* M */
64 pll_audio_sdm_table, BIT(24),
73 0, 4, /* M */
74 BIT(24), /* frac enable */
85 0, 4, /* M */
86 BIT(24), /* frac enable */
98 0, 2, /* M */
115 0, 4, /* M */
116 BIT(24), /* frac enable */
127 0, 4, /* M */
128 BIT(24), /* frac enable */
150 0, 4, /* M */
159 0, 4, /* M */
160 BIT(24), /* frac enable */
171 0, 4, /* M */
172 BIT(24), /* frac enable */
243 0, 5, /* M */
245 24, 2, /* mux */
283 0x060, BIT(24), 0);
320 0x064, BIT(24), 0);
363 0, 4, /* M */
365 24, 2, /* mux */
371 0, 4, /* M */
373 24, 2, /* mux */
379 0, 4, /* M */
381 24, 2, /* mux */
392 0, 4, /* M */
394 24, 2, /* mux */
405 0, 4, /* M */
407 24, 2, /* mux */
418 0, 4, /* M */
420 24, 2, /* mux */
430 0, 4, /* M */
432 24, 2, /* mux */
437 0, 4, /* M */
439 24, 2, /* mux */
444 0, 4, /* M */
446 24, 2, /* mux */
451 0, 4, /* M */
453 24, 2, /* mux */
457 0, 4, /* M */
459 24, 2, /* mux */
464 0, 4, /* M */
466 24, 2, /* mux */
497 0, 4, /* M */
499 24, 2, /* mux */
523 0x100, BIT(24), 0);
537 0x104, 0, 4, 24, 3, BIT(31), 0);
539 0x108, 0, 4, 24, 3, BIT(31), 0);
541 0x10c, 0, 4, 24, 3, BIT(31), 0);
543 0x110, 0, 4, 24, 3, BIT(31), 0);
548 0x114, 0, 4, 24, 3, BIT(31), 0);
554 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
556 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
562 0x12c, 0, 4, 24, 3, BIT(31),
565 0x130, 0, 4, 24, 3, BIT(31),
572 0x134, 16, 4, 24, 3, BIT(31), 0);
614 0x150, 0, 4, 24, 2, BIT(31),
624 0, 3, /* M */
626 24, 2, /* mux */
631 0, 3, /* M */
633 24, 2, /* mux */
638 0x168, 16, 3, 24, 2, BIT(31),
648 0x180, 0, 3, 24, 2, BIT(31), 0);
650 0x184, 0, 3, 24, 2, BIT(31), 0);
652 0x188, 0, 3, 24, 2, BIT(31), 0);
654 0x18c, 0, 3, 24, 2, BIT(31), 0);
667 .shift = 24,
686 .shift = 24,
705 .shift = 24,
721 0, 3, /* M */
722 24, 2, /* mux */
728 0, 3, /* M */
729 24, 2, /* mux */
745 .m = _SUNXI_CCU_DIV(8, 5),
748 .shift = 24,
766 .m = _SUNXI_CCU_DIV(8, 5),
769 .shift = 24,
787 .m = _SUNXI_CCU_DIV(8, 5),
790 .shift = 24,
1171 [RST_AHB1_OTG] = { 0x2c0, BIT(24) },
1190 [RST_AHB1_DEU1] = { 0x2c4, BIT(24) },
1226 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
1227 .bypass_index = 1, /* index of 24 MHz oscillator */