Lines Matching +full:24 +full:m
33 * The M factor is present in the register's description, but not in the
34 * frequency formula, and it's documented as "M is only used for backdoor
56 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
71 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
86 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
103 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
120 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
139 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
157 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
175 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
193 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
208 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
226 { .rate = 90316800, .pattern = 0xc001288d, .m = 3, .n = 22 },
227 { .rate = 98304000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
235 .m = _SUNXI_CCU_DIV(16, 6),
237 BIT(24), 0x178, BIT(31)),
252 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
261 0, 2, /* M */
263 24, 2, /* mux */
270 0, 2, /* M */
272 24, 2, /* mux */
276 0, 2, /* M */
278 24, 2, /* mux */
282 0, 2, /* M */
284 24, 2, /* mux */
290 0, 3, /* M */
291 24, 2, /* mux */
297 0, 4, /* M */
298 24, 1, /* mux */
308 0, 4, /* M */
309 24, 1, /* mux */
317 0, 4, /* M */
318 24, 1, /* mux */
327 0, 2, /* M */
328 24, 1, /* mux */
332 0, 2, /* M */
341 0, 4, /* M */
343 24, 1, /* mux */
352 0, 3, /* M */
353 24, 1, /* mux */
381 .mux = _SUNXI_CCU_MUX(24, 2),
411 0, 4, /* M */
413 24, 3, /* mux */
418 0, 4, /* M */
420 24, 3, /* mux */
429 0, 4, /* M */
431 24, 2, /* mux */
437 0, 4, /* M */
439 24, 2, /* mux */
445 0, 4, /* M */
447 24, 2, /* mux */
470 0, 4, /* M */
472 24, 3, /* mux */
477 0, 4, /* M */
479 24, 3, /* mux */
486 static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
494 0, 4, /* M */
496 24, 1, /* mux */
511 .mux = _SUNXI_CCU_MUX(24, 2),
526 .mux = _SUNXI_CCU_MUX(24, 2),
540 0, 4, /* M */
541 24, 2, /* mux */
546 0, 4, /* M */
547 24, 2, /* mux */
557 .mux = _SUNXI_CCU_MUX(24, 2),
570 * There are OHCI 12M clock source selection bits for the four USB 2.0 ports.
571 * We will force them to 0 (12M divided from 48M).
605 0, 4, /* M */
606 24, 2, /* mux */
622 .shift = 24,
650 0, 4, /* M */
652 24, 3, /* mux */
657 0, 4, /* M */
659 24, 3, /* mux */
670 0, 4, /* M */
672 24, 3, /* mux */
683 0, 4, /* M */
684 24, 2, /* mux */
1059 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1152 * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz) in sun50i_h616_ccu_probe()
1159 val &= ~GENMASK(25, 24); in sun50i_h616_ccu_probe()
1179 val |= BIT(24); in sun50i_h616_ccu_probe()