Lines Matching +full:24 +full:m
31 * The M factor is present in the register's description, but not in the
32 * frequency formula, and it's documented as "M is only used for backdoor
54 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
69 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
86 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
104 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
122 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
140 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
158 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
173 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
188 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
208 { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
209 { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
216 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
218 BIT(24), 0x178, BIT(31)),
231 0x500, 24, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
240 0, 2, /* M */
242 24, 2, /* mux */
249 0, 2, /* M */
251 24, 2, /* mux */
255 0, 2, /* M */
257 24, 2, /* mux */
261 0, 2, /* M */
263 24, 2, /* mux */
269 0, 3, /* M */
270 24, 2, /* mux */
276 0, 4, /* M */
277 24, 1, /* mux */
289 0, 4, /* M */
290 24, 1, /* mux */
300 24, 1, /* mux */
310 0, 4, /* M */
312 24, 1, /* mux */
321 0, 3, /* M */
322 24, 1, /* mux */
330 0, 4, /* M */
332 24, 1, /* mux */
341 0, 3, /* M */
342 24, 1, /* mux */
376 .mux = _SUNXI_CCU_MUX(24, 2),
408 0, 4, /* M */
410 24, 3, /* mux */
415 0, 4, /* M */
417 24, 3, /* mux */
426 0, 4, /* M */
428 24, 2, /* mux */
434 0, 4, /* M */
436 24, 2, /* mux */
442 0, 4, /* M */
444 24, 2, /* mux */
467 0, 4, /* M */
469 24, 3, /* mux */
474 0, 4, /* M */
476 24, 3, /* mux */
487 0, 4, /* M */
489 24, 1, /* mux */
497 0, 4, /* M */
499 24, 1, /* mux */
511 .mux = _SUNXI_CCU_MUX(24, 2),
524 .mux = _SUNXI_CCU_MUX(24, 2),
537 .mux = _SUNXI_CCU_MUX(24, 2),
550 .mux = _SUNXI_CCU_MUX(24, 2),
568 .mux = _SUNXI_CCU_MUX(24, 2),
583 .mux = _SUNXI_CCU_MUX(24, 2),
598 .mux = _SUNXI_CCU_MUX(24, 2),
611 * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports.
612 * We will force them to 0 (12M divided from 48M).
624 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 0xa7c, BIT(27), 0);
635 static CLK_FIXED_FACTOR_HW(pcie_ref_100m_clk, "pcie-ref-100M",
636 &pll_periph0_4x_clk.hw, 24, 1, 0);
637 static SUNXI_CCU_GATE(pcie_ref_clk, "pcie-ref", "pcie-ref-100M",
644 0, 4, /* M */
649 0, 5, /* M */
659 0, 4, /* M */
660 24, 2, /* mux */
676 .shift = 24,
703 24, 3, /* mux */
716 0, 4, /* M */
718 24, 3, /* mux */
732 0, 4, /* M */
733 24, 3, /* mux */
741 0, 5, /* M */
742 24, 3, /* mux */
750 0, 4, /* M */
751 24, 2, /* mux */
765 * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
770 24, 1, CLK_SET_RATE_PARENT);
1136 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1188 .bypass_index = 0, /* index of 24 MHz oscillator */
1234 * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz) in sun50i_h6_ccu_probe()
1241 val &= ~GENMASK(25, 24); in sun50i_h6_ccu_probe()
1259 val |= BIT(24); in sun50i_h6_ccu_probe()