Lines Matching +full:24 +full:m
31 .m = _SUNXI_CCU_DIV(0, 2),
57 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
58 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
64 0, 5, /* M */
65 pll_audio_sdm_table, BIT(24),
76 0, 4, /* M */
77 BIT(24), /* frac enable */
88 0, 4, /* M */
89 BIT(24), /* frac enable */
101 0, 2, /* M */
139 0, 4, /* M */
140 BIT(24), /* frac enable */
151 0, 4, /* M */
152 BIT(24), /* frac enable */
178 .m = _SUNXI_CCU_DIV(0, 4),
195 0, 4, /* M */
196 BIT(24), /* frac enable */
207 0, 4, /* M */
208 BIT(24), /* frac enable */
219 0, 2, /* M */
271 0, 5, /* M */
273 24, 2, /* mux */
327 0x060, BIT(24), 0);
404 .mux = _SUNXI_CCU_MUX(24, 2),
417 0, 4, /* M */
419 24, 2, /* mux */
438 0, 4, /* M */
440 24, 2, /* mux */
447 0, 4, /* M */
449 24, 2, /* mux */
456 0, 4, /* M */
458 24, 2, /* mux */
465 0, 4, /* M */
467 24, 4, /* mux */
472 0, 4, /* M */
474 24, 2, /* mux */
479 0, 4, /* M */
481 24, 2, /* mux */
486 0, 4, /* M */
488 24, 2, /* mux */
512 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",
534 0x104, 0, 4, 24, 3, BIT(31),
546 tcon0_table, 0x118, 24, 3, BIT(31),
553 0, 4, /* M */
554 24, 2, /* mux */
560 0x124, 0, 4, 24, 3, BIT(31), 0);
567 0x134, 16, 4, 24, 3, BIT(31), 0);
587 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
595 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
883 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
941 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
942 .bypass_index = 1, /* index of 24 MHz oscillator */