Lines Matching +full:24 +full:m
25 #define SUN50I_A100_PLL_SDM_ENABLE BIT(24)
39 * The M factor is present in the register's description, but not in the
40 * frequency formula, and it's documented as "M is only used for backdoor
62 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
78 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
95 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
113 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
132 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
148 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
164 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
180 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
191 * The COM PLL has m0 dividers in addition to the usual N, M
197 { .rate = 451584000, .pattern = 0xc0014396, .m = 2, .n = 37 },
204 .m = _SUNXI_CCU_DIV(0, 1),
205 .sdm = _SUNXI_CCU_SDM(pll_com_sdm_table, BIT(24),
221 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
233 * The Audio PLL has m0, m1 dividers in addition to the usual N, M
240 { .rate = 45158400, .pattern = 0xc001bcd3, .m = 18, .n = 33 },
241 { .rate = 49152000, .pattern = 0xc001eb85, .m = 20, .n = 40 },
242 { .rate = 180633600, .pattern = 0xc001288d, .m = 3, .n = 22 },
243 { .rate = 196608000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
250 .m = _SUNXI_CCU_DIV(16, 6),
252 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
268 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
277 0, 2, /* M */
279 24, 3, /* mux */
287 0, 2, /* M */
289 24, 3, /* mux */
293 0, 2, /* M */
295 24, 3, /* mux */
299 0, 2, /* M */
301 24, 3, /* mux */
308 0, 3, /* M */
309 24, 2, /* mux */
315 0, 4, /* M */
316 24, 1, /* mux */
329 0, 4, /* M */
330 24, 3, /* mux */
339 0, 2, /* M */
340 24, 1, /* mux */
349 0, 4, /* M */
351 24, 1, /* mux */
360 0, 3, /* M */
361 24, 1, /* mux */
416 0, 4, /* M */
418 24, 3, /* mux */
423 0, 4, /* M */
425 24, 3, /* mux */
434 0, 4, /* M */
436 24, 2, /* mux */
442 0, 4, /* M */
444 24, 2, /* mux */
450 0, 4, /* M */
452 24, 2, /* mux */
473 0, 4, /* M */
475 24, 3, /* mux */
480 0, 4, /* M */
482 24, 3, /* mux */
487 0, 4, /* M */
489 24, 3, /* mux */
497 static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
505 0, 4, /* M */
507 24, 3, /* mux */
514 0, 4, /* M */
516 24, 3, /* mux */
530 .mux = _SUNXI_CCU_MUX(24, 2),
543 .mux = _SUNXI_CCU_MUX(24, 2),
556 .mux = _SUNXI_CCU_MUX(24, 2),
569 .mux = _SUNXI_CCU_MUX(24, 2),
587 .mux = _SUNXI_CCU_MUX(24, 2),
602 .mux = _SUNXI_CCU_MUX(24, 2),
616 0, 4, /* M */
617 24, 2, /* mux */
623 0, 4, /* M */
624 24, 2, /* mux */
630 0, 4, /* M */
631 24, 2, /* mux */
639 * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports.
640 * We will force them to 0 (12M divided from 48M).
670 0, 4, /* M */
671 24, 2, /* mux */
685 0, 4, /* M */
687 24, 3, /* mux */
698 0, 4, /* M */
700 24, 3, /* mux */
713 0, 4, /* M */
714 24, 3, /* mux */
723 0, 5, /* M */
724 24, 3, /* mux */
733 0, 5, /* M */
734 24, 3, /* mux */
747 0, 5, /* M */
748 24, 3, /* mux */
1116 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1238 * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz) in sun50i_a100_ccu_probe()
1245 val &= ~GENMASK(25, 24); in sun50i_a100_ccu_probe()