Lines Matching +full:24 +full:m
55 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
70 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
84 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
106 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
130 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
154 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
165 * PLL_AUDIO0 has m0, m1 dividers in addition to the usual N, M factors.
168 * The M factor must be an even number to produce a 50% duty cycle output.
172 { .rate = 90316800, .pattern = 0xc001288d, .m = 6, .n = 22 },
179 .m = _SUNXI_CCU_DIV(16, 6),
180 .sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
210 .m = _SUNXI_CCU_DIV(1, 1),
243 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
258 0, 2, /* M */
260 24, 2, /* mux */
270 0, 5, /* M */
272 24, 2, /* mux */
276 0, 5, /* M */
278 24, 2, /* mux */
292 0, 5, /* M */
293 24, 3, /* mux */
301 0, 5, /* M */
302 24, 3, /* mux */
310 0, 5, /* M */
311 24, 3, /* mux */
324 0, 4, /* M */
326 24, 3, /* mux */
338 0, 5, /* M */
339 24, 1, /* mux */
381 0, 2, /* M */
383 24, 2, /* mux */
416 0, 4, /* M */
418 24, 3, /* mux */
423 0, 4, /* M */
425 24, 3, /* mux */
437 0, 4, /* M */
439 24, 3, /* mux */
485 0, 4, /* M */
487 24, 3, /* mux */
492 0, 4, /* M */
494 24, 3, /* mux */
503 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25M_clk, "emac-25M", pll_periph0_hws,
504 0x970, BIT(31) | BIT(30), 24, 0);
514 0, 4, /* M */
516 24, 3, /* mux */
536 0, 5, /* M */
538 24, 3, /* mux */
543 0, 5, /* M */
545 24, 3, /* mux */
550 0, 5, /* M */
552 24, 3, /* mux */
563 0, 5, /* M */
565 24, 3, /* mux */
577 0, 5, /* M */
579 24, 3, /* mux */
589 0, 5, /* M */
591 24, 3, /* mux */
604 0, 5, /* M */
606 24, 3, /* mux */
614 0, 5, /* M */
616 24, 3, /* mux */
621 0, 5, /* M */
623 24, 3, /* mux */
649 .shift = 24,
667 .shift = 24,
699 static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M,
711 24, 1, /* mux */
726 0, 4, /* M */
727 24, 3, /* mux */
743 0, 4, /* M */
745 24, 3, /* mux */
753 0, 4, /* M */
755 24, 3, /* mux */
763 0, 4, /* M */
765 24, 3, /* mux */
781 0, 5, /* M */
782 24, 3, /* mux */
792 0, 4, /* M */
794 24, 1, /* mux */
807 0, 4, /* M */
808 24, 3, /* mux */
821 0, 5, /* M */
822 24, 3, /* mux */
834 24, 3, /* mux */
852 0, 5, /* M */
853 24, 3, /* mux */
874 0, 5, /* M */
875 24, 3, /* mux */
891 static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
893 static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
895 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph0_2x_hws,
897 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph0_hws,
898 0xf30, BIT(3), 24, 0);
908 static SUNXI_CCU_M_HW_WITH_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M_parents, 0xf34,
909 0, 5, /* M */
910 24, 2, /* mux */
915 0, 5, /* M */
1284 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1356 /* Force PLL_CPUX factor M to 0. */ in sun20i_d1_ccu_probe()
1377 /* Force fanout-27M factor N to 0. */ in sun20i_d1_ccu_probe()