Lines Matching full:parents
465 struct clk_parent_data parents[4] = {}; in jh7110_syscrg_probe() local
469 .parent_data = parents, in jh7110_syscrg_probe()
478 unsigned int pidx = jh7110_sysclk_data[idx].parents[i]; in jh7110_syscrg_probe()
481 parents[i].hw = &priv->reg[pidx].hw; in jh7110_syscrg_probe()
483 parents[i].fw_name = "osc"; in jh7110_syscrg_probe()
485 parents[i].fw_name = "gmac1_rmii_refin"; in jh7110_syscrg_probe()
487 parents[i].fw_name = "gmac1_rgmii_rxin"; in jh7110_syscrg_probe()
489 parents[i].fw_name = "i2stx_bclk_ext"; in jh7110_syscrg_probe()
491 parents[i].fw_name = "i2stx_lrck_ext"; in jh7110_syscrg_probe()
493 parents[i].fw_name = "i2srx_bclk_ext"; in jh7110_syscrg_probe()
495 parents[i].fw_name = "i2srx_lrck_ext"; in jh7110_syscrg_probe()
497 parents[i].fw_name = "tdm_ext"; in jh7110_syscrg_probe()
499 parents[i].fw_name = "mclk_ext"; in jh7110_syscrg_probe()
501 parents[i].fw_name = "pll0_out"; in jh7110_syscrg_probe()
503 parents[i].fw_name = "pll1_out"; in jh7110_syscrg_probe()
505 parents[i].fw_name = "pll2_out"; in jh7110_syscrg_probe()
507 parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT]; in jh7110_syscrg_probe()