Lines Matching +full:3 +full:d400000
63 #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3
66 #define SPEAR1310_GMAC_PHY_CLK_SHIFT 3
82 #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3
130 #define SPEAR1310_SYSRAM0_CLK_ENB 3
142 #define SPEAR1310_KBD_CLK_ENB 3
163 #define SPEAR1310_OSC_32K_CLK_ENB 3
170 #define SPEAR1310_SSP1_CLK_MASK 3
222 #define SPEAR1310_MII2_CLK_ENB 3
256 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
265 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
320 {.xscale = 1, .yscale = 3, .eq = 0},
942 clk_register_clkdev(clk, "stmmacphy.3", NULL); in spear1310_clk_init()
1085 clk_register_clkdev(clk, NULL, "5d400000.spi"); in spear1310_clk_init()