72  * struct sg2042_divider_clock - Divider clock
79  * @offset_ctrl:	offset of divider control registers
80  * @shift:		shift of "Clock Divider Factor" in divider control register
81  * @width:		width of "Clock Divider Factor" in divider control register
83  * @initval:		In the divider control register, we can configure whether
84  *			to use the value of "Clock Divider Factor" or just use
89  *			value when poweron) and default value of "Clock Divider
160 	struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);  in sg2042_clk_divider_recalc_rate()  local
164 	if (!(readl(divider->reg) & BIT(SHIFT_DIV_FACTOR_SEL))) {  in sg2042_clk_divider_recalc_rate()
165 		val = divider->initval;  in sg2042_clk_divider_recalc_rate()
167 		val = readl(divider->reg) >> divider->shift;  in sg2042_clk_divider_recalc_rate()
168 		val &= clk_div_mask(divider->width);  in sg2042_clk_divider_recalc_rate()
172 				       divider->div_flags, divider->width);  in sg2042_clk_divider_recalc_rate()
183 	struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);  in sg2042_clk_divider_round_rate()  local
188 	if (divider->div_flags & CLK_DIVIDER_READ_ONLY) {  in sg2042_clk_divider_round_rate()
189 		if (!(readl(divider->reg) & BIT(SHIFT_DIV_FACTOR_SEL))) {  in sg2042_clk_divider_round_rate()
190 			bestdiv = divider->initval;  in sg2042_clk_divider_round_rate()
192 			bestdiv = readl(divider->reg) >> divider->shift;  in sg2042_clk_divider_round_rate()
193 			bestdiv &= clk_div_mask(divider->width);  in sg2042_clk_divider_round_rate()
198 					      divider->width, divider->div_flags);  in sg2042_clk_divider_round_rate()
210 	struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);  in sg2042_clk_divider_set_rate()  local
215 				divider->width, divider->div_flags);  in sg2042_clk_divider_set_rate()
217 	if (divider->lock)  in sg2042_clk_divider_set_rate()
218 		spin_lock_irqsave(divider->lock, flags);  in sg2042_clk_divider_set_rate()
220 		__acquire(divider->lock);  in sg2042_clk_divider_set_rate()
224 	 * Assert to reset divider.  in sg2042_clk_divider_set_rate()
228 	val = readl(divider->reg);  in sg2042_clk_divider_set_rate()
232 	writel(val, divider->reg);  in sg2042_clk_divider_set_rate()
234 	if (divider->div_flags & CLK_DIVIDER_HIWORD_MASK) {  in sg2042_clk_divider_set_rate()
235 		val = clk_div_mask(divider->width) << (divider->shift + 16);  in sg2042_clk_divider_set_rate()
237 		val = readl(divider->reg);  in sg2042_clk_divider_set_rate()
238 		val &= ~(clk_div_mask(divider->width) << divider->shift);  in sg2042_clk_divider_set_rate()
240 	val |= value << divider->shift;  in sg2042_clk_divider_set_rate()
242 	writel(val, divider->reg);  in sg2042_clk_divider_set_rate()
247 	writel(val, divider->reg);  in sg2042_clk_divider_set_rate()
249 	if (divider->lock)  in sg2042_clk_divider_set_rate()
250 		spin_unlock_irqrestore(divider->lock, flags);  in sg2042_clk_divider_set_rate()
252 		__release(divider->lock);  in sg2042_clk_divider_set_rate()
504  * "clk_div_ddr01_0" is the name of Clock divider 0 control of DDR01, and
507  * "clk_div_ddr01_1" is the name of Clock divider 1 control of DDR01, and
624 	 * narrow for us to produce 115200. Use UART internal divider directly.
825 				pr_warn("divider value exceeds LOWORD field\n");  in sg2042_clk_register_divs()