Lines Matching +full:0 +full:x17400000
31 /* Register Offset definitions for CMU_TOP (0x1e080000) */
32 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
33 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
34 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
35 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
36 #define PLL_LOCKTIME_PLL_SPARE 0x0010
37 #define PLL_CON0_PLL_SHARED0 0x0100
38 #define PLL_CON1_PLL_SHARED0 0x0104
39 #define PLL_CON2_PLL_SHARED0 0x0108
40 #define PLL_CON3_PLL_SHARED0 0x010c
41 #define PLL_CON4_PLL_SHARED0 0x0110
42 #define PLL_CON0_PLL_SHARED1 0x0140
43 #define PLL_CON1_PLL_SHARED1 0x0144
44 #define PLL_CON2_PLL_SHARED1 0x0148
45 #define PLL_CON3_PLL_SHARED1 0x014c
46 #define PLL_CON4_PLL_SHARED1 0x0150
47 #define PLL_CON0_PLL_SHARED2 0x0180
48 #define PLL_CON1_PLL_SHARED2 0x0184
49 #define PLL_CON2_PLL_SHARED2 0x0188
50 #define PLL_CON3_PLL_SHARED2 0x018c
51 #define PLL_CON4_PLL_SHARED2 0x0190
52 #define PLL_CON0_PLL_SHARED3 0x01c0
53 #define PLL_CON1_PLL_SHARED3 0x01c4
54 #define PLL_CON2_PLL_SHARED3 0x01c8
55 #define PLL_CON3_PLL_SHARED3 0x01cc
56 #define PLL_CON4_PLL_SHARED3 0x01d0
57 #define PLL_CON0_PLL_SPARE 0x0200
58 #define PLL_CON1_PLL_SPARE 0x0204
59 #define PLL_CON2_PLL_SPARE 0x0208
60 #define PLL_CON3_PLL_SPARE 0x020c
61 #define PLL_CON4_PLL_SPARE 0x0210
62 #define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800
63 #define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810
64 #define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840
65 #define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844
66 #define CMU_HCHGEN_CLKMUX 0x0850
67 #define POWER_FAIL_DETECT_PLL 0x0864
68 #define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870
69 #define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874
70 #define EARLY_WAKEUP_APM_CTRL 0x0878
71 #define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c
72 #define EARLY_WAKEUP_DPU_CTRL 0x0880
73 #define EARLY_WAKEUP_CSIS_CTRL 0x0884
74 #define EARLY_WAKEUP_APM_DEST 0x0890
75 #define EARLY_WAKEUP_CLUSTER0_DEST 0x0894
76 #define EARLY_WAKEUP_DPU_DEST 0x0898
77 #define EARLY_WAKEUP_CSIS_DEST 0x089c
78 #define EARLY_WAKEUP_SW_TRIG_APM 0x08c0
79 #define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4
80 #define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8
81 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0
82 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4
83 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8
84 #define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0
85 #define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4
86 #define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8
87 #define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0
88 #define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4
89 #define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8
90 #define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000
91 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004
92 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008
93 #define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c
94 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010
95 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014
96 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018
97 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c
98 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020
99 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024
100 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028
101 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c
102 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030
103 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034
104 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038
105 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c
106 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040
107 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044
108 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048
109 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c
110 #define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050
111 #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054
112 #define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058
113 #define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c
114 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060
115 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064
116 #define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068
117 #define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c
118 #define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070
119 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074
120 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078
121 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c
122 #define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080
123 #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084
124 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088
125 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c
126 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090
127 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094
128 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098
129 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c
130 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0
131 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4
132 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8
133 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac
134 #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0
135 #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4
136 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8
137 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc
138 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0
139 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4
140 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8
141 #define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc
142 #define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0
143 #define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4
144 #define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8
145 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc
146 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0
147 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4
148 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8
149 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec
150 #define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0
151 #define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4
152 #define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8
153 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc
154 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100
155 #define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104
156 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108
157 #define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800
158 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804
159 #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808
160 #define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c
161 #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810
162 #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814
163 #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818
164 #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c
165 #define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820
166 #define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824
167 #define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828
168 #define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c
169 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830
170 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834
171 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
172 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
173 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840
174 #define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844
175 #define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848
176 #define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c
177 #define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850
178 #define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854
179 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858
180 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c
181 #define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860
182 #define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864
183 #define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868
184 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c
185 #define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870
186 #define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874
187 #define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878
188 #define CLK_CON_DIV_CLKCMU_HPM 0x187c
189 #define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880
190 #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884
191 #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888
192 #define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c
193 #define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890
194 #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894
195 #define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898
196 #define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c
197 #define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0
198 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4
199 #define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8
200 #define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac
201 #define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0
202 #define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4
203 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8
204 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc
205 #define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0
206 #define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4
207 #define CLK_CON_DIV_CLKCMU_OTP 0x18c8
208 #define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc
209 #define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0
210 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4
211 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8
212 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc
213 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0
214 #define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4
215 #define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8
216 #define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec
217 #define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0
218 #define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4
219 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8
220 #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc
221 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900
222 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904
223 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908
224 #define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c
225 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910
226 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914
227 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918
228 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c
229 #define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920
230 #define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000
231 #define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004
232 #define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008
233 #define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c
234 #define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010
235 #define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014
236 #define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018
237 #define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c
238 #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020
239 #define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024
240 #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028
241 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c
242 #define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030
243 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034
244 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038
245 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c
246 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040
247 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044
248 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048
249 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c
250 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050
251 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054
252 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058
253 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c
254 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060
255 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064
256 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068
257 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c
258 #define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070
259 #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074
260 #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078
261 #define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c
262 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080
263 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084
264 #define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088
265 #define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c
266 #define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090
267 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094
268 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098
269 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c
270 #define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0
271 #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4
272 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8
273 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac
274 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0
275 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4
276 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8
277 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc
278 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0
279 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4
280 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8
281 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc
282 #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0
283 #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4
284 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8
285 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc
286 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0
287 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4
288 #define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8
289 #define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec
290 #define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0
291 #define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4
292 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8
293 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc
294 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100
295 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104
296 #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108
297 #define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c
298 #define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110
299 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114
300 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118
301 #define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c
302 #define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000
303 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004
304 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008
305 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c
306 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010
307 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014
308 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018
309 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c
310 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020
311 #define DMYQCH_CON_OTP_QCH 0x3024
312 #define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00
313 #define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10
314 #define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14
315 #define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18
316 #define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c
317 #define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20
318 #define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24
319 #define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28
320 #define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c
321 #define MIFMIRROR_QUEUE_CTRL_REG 0x3e00
322 #define MIFMIRROR_QUEUE_ENTRY0 0x3e10
323 #define MIFMIRROR_QUEUE_ENTRY1 0x3e14
324 #define MIFMIRROR_QUEUE_ENTRY2 0x3e18
325 #define MIFMIRROR_QUEUE_ENTRY3 0x3e1c
326 #define MIFMIRROR_QUEUE_ENTRY4 0x3e20
327 #define MIFMIRROR_QUEUE_ENTRY5 0x3e24
328 #define MIFMIRROR_QUEUE_ENTRY6 0x3e28
329 #define MIFMIRROR_QUEUE_ENTRY7 0x3e2c
330 #define MIFMIRROR_QUEUE_BUSY 0x3e30
331 #define GENERALIO_ACD_CHANNEL_0 0x3f00
332 #define GENERALIO_ACD_CHANNEL_1 0x3f04
333 #define GENERALIO_ACD_CHANNEL_2 0x3f08
334 #define GENERALIO_ACD_CHANNEL_3 0x3f0c
335 #define GENERALIO_ACD_MASK 0x3f14
962 CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 3),
964 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 3),
966 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 3),
968 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 3),
970 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 3),
972 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 3),
974 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 3),
976 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 3),
978 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 3),
980 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 3),
982 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 3),
984 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 3),
986 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
989 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0, 1),
991 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
993 mout_cmu_cpucl0_dbg_p, CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
996 0, 3),
999 0, 3),
1002 0, 3),
1004 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 3),
1006 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 3),
1008 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3),
1010 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3),
1012 CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 0, 3),
1014 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
1016 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 3),
1018 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 3),
1020 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 3),
1022 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 3),
1024 mout_cmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 3),
1026 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 3),
1028 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 3),
1030 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 3),
1032 CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
1034 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3),
1036 mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
1039 0, 1),
1042 0, 1),
1044 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3),
1046 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1),
1048 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 3),
1051 0, 2),
1053 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1),
1056 0, 2),
1058 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3),
1060 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3),
1062 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 3),
1064 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3),
1066 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 3),
1068 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
1070 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
1072 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
1074 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
1076 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 3),
1078 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 3),
1080 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
1082 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
1084 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 2),
1086 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 2),
1088 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
1091 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0, 1),
1093 mout_cmu_top_cmuref_p, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0, 2),
1095 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 3),
1097 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 3),
1099 mout_cmu_tpu_tpuctl_p, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 3),
1101 CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
1103 CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
1108 CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
1110 CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
1112 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
1114 CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
1116 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5),
1118 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5),
1120 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5),
1122 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5),
1124 CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5),
1126 CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5),
1128 CLK_CON_DIV_CLKCMU_CIS_CLK6, 0, 5),
1130 CLK_CON_DIV_CLKCMU_CIS_CLK7, 0, 5),
1132 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
1134 "gout_cmu_cpucl0_dbg", CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
1136 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
1138 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
1140 "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
1142 CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
1144 CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
1146 CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
1148 CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
1150 CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
1152 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
1154 CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
1156 CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
1158 CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
1160 CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
1162 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
1164 CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
1166 CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
1168 CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
1170 CLK_CON_DIV_CLKCMU_HPM, 0, 2),
1172 CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
1174 "gout_cmu_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
1176 "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
1178 CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
1180 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
1182 CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
1184 "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
1186 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
1188 "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
1190 CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
1192 CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
1194 CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
1196 CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
1198 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
1200 CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
1202 CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
1204 CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
1206 CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
1208 CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4),
1210 "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
1212 CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
1214 "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
1216 CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
1218 CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
1220 CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
1222 CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
1224 "gout_cmu_tpu_tpuctl", CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
1226 CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
1228 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
1230 CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),
1232 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
1234 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
1236 "dout_cmu_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
1238 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
1240 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
1242 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
1244 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
1246 "mout_pll_shared2", CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
1248 "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
1253 "gout_cmu_hsi0_usbdpdbg", 1, 4, 0),
1254 FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0),
1259 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0),
1261 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0),
1263 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0),
1265 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0),
1268 21, 0, 0),
1271 21, 0, 0),
1274 21, 0, 0),
1277 21, 0, 0),
1279 "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
1281 CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
1283 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
1285 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
1287 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
1289 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),
1291 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),
1293 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),
1295 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),
1297 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0),
1299 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0),
1301 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0),
1303 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0),
1305 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
1307 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
1310 21, 0, 0),
1313 21, 0, 0),
1316 21, 0, 0),
1319 21, 0, 0),
1321 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
1323 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
1325 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
1327 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
1329 CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
1331 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
1333 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
1335 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
1337 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
1339 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
1342 21, 0, 0),
1344 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
1346 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
1348 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
1350 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
1352 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
1355 21, 0, 0),
1358 21, 0, 0),
1361 21, 0, 0),
1363 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
1365 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
1367 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
1370 21, 0, 0),
1372 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
1375 21, 0, 0),
1377 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
1379 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
1381 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
1383 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
1385 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
1387 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
1389 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
1391 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
1393 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
1395 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
1398 21, 0, 0),
1400 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
1403 21, 0, 0),
1405 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
1407 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
1410 21, 0, 0),
1412 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
1414 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
1417 21, 0, 0),
1419 CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
1449 /* Register Offset definitions for CMU_APM (0x17400000) */
1450 #define APM_CMU_APM_CONTROLLER_OPTION 0x0800
1451 #define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810
1452 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000
1453 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004
1454 #define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800
1455 #define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804
1456 #define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808
1457 #define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c
1458 #define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000
1459 #define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004
1460 #define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008
1461 #define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c
1462 #define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010
1463 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014
1464 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018
1465 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c
1466 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020
1467 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024
1468 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028
1469 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c
1470 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030
1471 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034
1472 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038
1473 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c
1474 #define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040
1475 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044
1476 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048
1477 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c
1478 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050
1479 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054
1480 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058
1481 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c
1482 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060
1483 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064
1484 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068
1485 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c
1486 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070
1487 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074
1488 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c
1489 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080
1490 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084
1491 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088
1492 #define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c
1493 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090
1494 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094
1495 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098
1496 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c
1497 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0
1498 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4
1499 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8
1500 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac
1501 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0
1502 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4
1503 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8
1504 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc
1505 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0
1506 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4
1507 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc
1508 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0
1509 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4
1510 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8
1511 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc
1512 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0
1513 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4
1514 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8
1515 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec
1516 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0
1517 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4
1518 #define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8
1519 #define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc
1520 #define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000
1521 #define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004
1522 #define PCH_CON_LHM_AXI_P_APM_PCH 0x3008
1523 #define PCH_CON_LHS_AXI_D_APM_PCH 0x300c
1524 #define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010
1525 #define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014
1526 #define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018
1527 #define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c
1528 #define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020
1529 #define QCH_CON_APBIF_RTC_QCH 0x3024
1530 #define QCH_CON_APBIF_TRTC_QCH 0x3028
1531 #define QCH_CON_APM_CMU_APM_QCH 0x302c
1532 #define QCH_CON_APM_USI0_UART_QCH 0x3030
1533 #define QCH_CON_APM_USI0_USI_QCH 0x3034
1534 #define QCH_CON_APM_USI1_UART_QCH 0x3038
1535 #define QCH_CON_D_TZPC_APM_QCH 0x303c
1536 #define QCH_CON_GPC_APM_QCH 0x3040
1537 #define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044
1538 #define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048
1539 #define QCH_CON_INTMEM_QCH 0x304c
1540 #define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050
1541 #define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054
1542 #define QCH_CON_LHM_AXI_P_APM_QCH 0x3058
1543 #define QCH_CON_LHS_AXI_D_APM_QCH 0x305c
1544 #define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060
1545 #define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064
1546 #define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068
1547 #define QCH_CON_MAILBOX_APM_AP_QCH 0x306c
1548 #define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070
1549 #define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078
1550 #define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c
1551 #define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080
1552 #define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084
1553 #define QCH_CON_PMU_INTR_GEN_QCH 0x3088
1554 #define QCH_CON_ROM_CRC32_HOST_QCH 0x308c
1555 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090
1556 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094
1557 #define QCH_CON_SPEEDY_APM_QCH 0x3098
1558 #define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c
1559 #define QCH_CON_SSMT_D_APM_QCH 0x30a0
1560 #define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4
1561 #define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8
1562 #define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac
1563 #define QCH_CON_SYSMMU_D_APM_QCH 0x30b0
1564 #define QCH_CON_SYSREG_APM_QCH 0x30b8
1565 #define QCH_CON_UASC_APM_QCH 0x30bc
1566 #define QCH_CON_UASC_DBGCORE_QCH 0x30c0
1567 #define QCH_CON_UASC_G_SWD_QCH 0x30c4
1568 #define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8
1569 #define QCH_CON_UASC_P_APM_QCH 0x30cc
1570 #define QCH_CON_WDT_APM_QCH 0x30d0
1571 #define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00
1652 FRATE(CLK_APM_PLL_DIV2_APM, "pll_alv_div2_apm", NULL, 0, 393216000),
1653 FRATE(CLK_APM_PLL_DIV4_APM, "pll_alv_div4_apm", NULL, 0, 196608000),
1654 FRATE(CLK_APM_PLL_DIV16_APM, "pll_alv_div16_apm", NULL, 0, 49152000),
1666 CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
1668 CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
1670 CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
1672 CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
1678 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 21, 0, 0),
1680 "dout_apm_boost", CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 21, 0, 0),
1682 "dout_apm_boost", CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 21, 0, 0),
1684 "dout_apm_boost", CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 21, 0, 0),
1686 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
1690 21, 0, 0),
1694 21, 0, 0),
1698 21, 0, 0),
1701 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0),
1704 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0),
1708 21, 0, 0),
1712 21, 0, 0),
1716 21, 0, 0),
1720 21, 0, 0),
1724 21, 0, 0),
1728 21, 0, 0),
1731 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1734 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1738 21, 0, 0),
1741 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 21, 0, 0),
1744 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 21, 0, 0),
1748 21, 0, 0),
1752 21, 0, 0),
1756 21, 0, 0),
1760 21, 0, 0),
1764 21, 0, 0),
1769 21, 0, 0),
1773 21, 0, 0),
1777 21, 0, 0),
1781 21, 0, 0),
1785 21, 0, 0),
1789 21, 0, 0),
1793 21, 0, 0),
1797 21, 0, 0),
1801 21, 0, 0),
1805 21, 0, 0),
1809 21, 0, 0),
1813 21, 0, 0),
1818 21, 0, 0),
1823 21, 0, 0),
1828 21, 0, 0),
1831 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 21, 0, 0),
1835 21, 0, 0),
1838 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 21, 0, 0),
1841 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 21, 0, 0),
1845 21, 0, 0),
1849 21, 0, 0),
1854 21, 0, 0),
1858 21, 0, 0),
1861 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 21, 0, 0),
1864 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 21, 0, 0),
1867 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1871 21, 0, 0),
1875 21, 0, 0),
1878 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 21, 0, 0),
1881 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),
1885 21, 0, 0),
1888 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),
1891 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0),
1894 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, CLK_IS_CRITICAL, 0),
1897 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0),
1900 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0),
1919 /* Register Offset definitions for CMU_HSI0 (0x11000000) */
1920 #define PLL_LOCKTIME_PLL_USB 0x0004
1921 #define PLL_CON0_PLL_USB 0x0140
1922 #define PLL_CON1_PLL_USB 0x0144
1923 #define PLL_CON2_PLL_USB 0x0148
1924 #define PLL_CON3_PLL_USB 0x014c
1925 #define PLL_CON4_PLL_USB 0x0150
1926 #define PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER 0x0600
1927 #define PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER 0x0604
1928 #define PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER 0x0610
1929 #define PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER 0x0614
1930 #define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER 0x0620
1931 #define PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER 0x0624
1932 #define PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER 0x0630
1933 #define PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER 0x0634
1934 #define PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER 0x0640
1935 #define PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER 0x0644
1936 #define PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0650
1937 #define PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0654
1938 #define PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0660
1939 #define PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0664
1940 #define HSI0_CMU_HSI0_CONTROLLER_OPTION 0x0800
1941 #define CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0 0x0810
1942 #define CLK_CON_MUX_MUX_CLK_HSI0_BUS 0x1000
1943 #define CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF 0x1004
1944 #define CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD 0x1008
1945 #define CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD 0x1800
1946 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK 0x2000
1947 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26 0x2004
1948 #define CLK_CON_GAT_CLK_HSI0_ALT 0x2008
1949 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK 0x200c
1950 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x2010
1951 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK 0x2014
1952 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK 0x2018
1953 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK 0x201c
1954 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK 0x2020
1955 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK 0x2024
1956 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK 0x2028
1957 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK 0x202c
1958 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK 0x2030
1959 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK 0x2034
1960 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK 0x2038
1961 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK 0x203c
1962 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK 0x2040
1963 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK 0x2044
1964 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK 0x2048
1965 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK 0x204c
1966 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK 0x2050
1967 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2 0x2054
1968 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK 0x2058
1969 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK 0x205c
1970 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK 0x2060
1971 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK 0x2064
1972 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK 0x2068
1973 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL 0x206c
1974 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY 0x2070
1975 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26 0x2074
1976 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40 0x2078
1977 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL 0x207c
1978 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK 0x2080
1979 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK 0x2084
1980 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK 0x2088
1981 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK 0x208c
1982 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK 0x2090
1983 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK 0x2094
1984 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK 0x2098
1985 #define DMYQCH_CON_USB31DRD_QCH 0x3000
1986 #define DMYQCH_CON_USB31DRD_QCH_REF 0x3004
1987 #define PCH_CON_LHM_AXI_G_ETR_HSI0_PCH 0x3008
1988 #define PCH_CON_LHM_AXI_P_AOCHSI0_PCH 0x300c
1989 #define PCH_CON_LHM_AXI_P_HSI0_PCH 0x3010
1990 #define PCH_CON_LHS_ACEL_D_HSI0_PCH 0x3014
1991 #define PCH_CON_LHS_AXI_D_HSI0AOC_PCH 0x3018
1992 #define QCH_CON_DP_LINK_QCH_GTC_CLK 0x301c
1993 #define QCH_CON_DP_LINK_QCH_PCLK 0x3020
1994 #define QCH_CON_D_TZPC_HSI0_QCH 0x3024
1995 #define QCH_CON_ETR_MIU_QCH_ACLK 0x3028
1996 #define QCH_CON_ETR_MIU_QCH_PCLK 0x302c
1997 #define QCH_CON_GPC_HSI0_QCH 0x3030
1998 #define QCH_CON_HSI0_CMU_HSI0_QCH 0x3034
1999 #define QCH_CON_LHM_AXI_G_ETR_HSI0_QCH 0x3038
2000 #define QCH_CON_LHM_AXI_P_AOCHSI0_QCH 0x303c
2001 #define QCH_CON_LHM_AXI_P_HSI0_QCH 0x3040
2002 #define QCH_CON_LHS_ACEL_D_HSI0_QCH 0x3044
2003 #define QCH_CON_LHS_AXI_D_HSI0AOC_QCH 0x3048
2004 #define QCH_CON_PPMU_HSI0_AOC_QCH 0x304c
2005 #define QCH_CON_PPMU_HSI0_BUS0_QCH 0x3050
2006 #define QCH_CON_SSMT_USB_QCH 0x3054
2007 #define QCH_CON_SYSMMU_USB_QCH 0x3058
2008 #define QCH_CON_SYSREG_HSI0_QCH 0x305c
2009 #define QCH_CON_UASC_HSI0_CTRL_QCH 0x3060
2010 #define QCH_CON_UASC_HSI0_LINK_QCH 0x3064
2011 #define QCH_CON_USB31DRD_QCH_APB 0x3068
2012 #define QCH_CON_USB31DRD_QCH_DBG 0x306c
2013 #define QCH_CON_USB31DRD_QCH_PCS 0x3070
2014 #define QCH_CON_USB31DRD_QCH_SLV_CTRL 0x3074
2015 #define QCH_CON_USB31DRD_QCH_SLV_LINK 0x3078
2016 #define QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0 0x3c00
2177 CLK_CON_MUX_MUX_CLK_HSI0_BUS, 0, 1),
2180 CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF, 0, 1),
2183 CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD, 0, 2),
2189 CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD, 0, 3),
2197 21, CLK_IGNORE_UNUSED, 0),
2202 21, 0, 0),
2205 CLK_CON_GAT_CLK_HSI0_ALT, 21, 0, 0),
2209 21, 0, 0),
2212 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, 21, 0, 0),
2216 21, 0, 0),
2219 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, 21, 0, 0),
2222 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, 21, 0, 0),
2225 CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, 21, 0, 0),
2229 21, 0, 0),
2233 21, 0, 0),
2238 21, CLK_IGNORE_UNUSED, 0),
2243 21, CLK_IGNORE_UNUSED, 0),
2247 21, 0, 0),
2251 21, 0, 0),
2255 21, 0, 0),
2259 21, 0, 0),
2263 21, 0, 0),
2267 21, 0, 0),
2272 21, CLK_IGNORE_UNUSED, 0),
2277 21, CLK_IGNORE_UNUSED, 0),
2282 21, CLK_IGNORE_UNUSED, 0),
2286 21, 0, 0),
2290 21, 0, 0),
2294 21, 0, 0),
2298 21, 0, 0),
2302 21, 0, 0),
2306 21, 0, 0),
2310 21, 0, 0),
2314 21, 0, 0),
2318 21, 0, 0),
2323 21, 0, 0),
2327 21, 0, 0),
2331 21, 0, 0),
2335 21, 0, 0),
2339 21, 0, 0),
2344 21, CLK_IGNORE_UNUSED, 0),
2349 21, CLK_IGNORE_UNUSED, 0),
2354 21, CLK_IGNORE_UNUSED, 0),
2358 FRATE(0, "tcxo_hsi1_hsi0", NULL, 0, 26000000),
2359 FRATE(0, "usb20phy_phy_clock", NULL, 0, 120000000),
2361 FRATE(0, "ioclk_clk_hsi0_alt", NULL, 0, 213000000),
2383 /* Register Offset definitions for CMU_HSI2 (0x14400000) */
2384 #define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER 0x0600
2385 #define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER 0x0604
2386 #define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0610
2387 #define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0614
2388 #define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER 0x0620
2389 #define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER 0x0624
2390 #define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0630
2391 #define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0634
2392 #define HSI2_CMU_HSI2_CONTROLLER_OPTION 0x0800
2393 #define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 0x0810
2394 …N_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2000
2395 …N_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004
2396 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK 0x2008
2397 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK 0x200c
2398 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK 0x2010
2399 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK 0x2014
2400 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK 0x201c
2401 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK 0x2020
2402 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK 0x2024
2403 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK 0x2028
2404 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK 0x202c
2405 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK 0x2030
2406 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034
2407 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038
2408 …GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c
2409 …AT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040
2410 …GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044
2411 …AT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048
2412 …GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x204c
2413 …AT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2050
2414 …GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2054
2415 …AT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2058
2416 … CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK 0x205c
2417 …AT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x2060
2418 …CIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2064
2419 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK 0x2068
2420 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK 0x206c
2421 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK 0x2070
2422 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK 0x2074
2423 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK 0x2078
2424 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK 0x207c
2425 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK 0x2080
2426 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK 0x2084
2427 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK 0x2088
2428 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK 0x208c
2429 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK 0x2090
2430 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK 0x2094
2431 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK 0x2098
2432 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK 0x209c
2433 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK 0x20a0
2434 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK 0x20a4
2435 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2 0x20a8
2436 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK 0x20ac
2437 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK 0x20b0
2438 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK 0x20b4
2439 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK 0x20b8
2440 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK 0x20bc
2441 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK 0x20c0
2442 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK 0x20c4
2443 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK 0x20c8
2444 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK 0x20cc
2445 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x20d0
2446 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x20d4
2447 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x20d8
2448 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK 0x20dc
2449 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK 0x20e0
2450 #define DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1 0x3000
2451 #define PCH_CON_LHM_AXI_P_HSI2_PCH 0x3008
2452 #define PCH_CON_LHS_ACEL_D_HSI2_PCH 0x300c
2453 #define QCH_CON_D_TZPC_HSI2_QCH 0x3010
2454 #define QCH_CON_GPC_HSI2_QCH 0x3014
2455 #define QCH_CON_GPIO_HSI2_QCH 0x3018
2456 #define QCH_CON_HSI2_CMU_HSI2_QCH 0x301c
2457 #define QCH_CON_LHM_AXI_P_HSI2_QCH 0x3020
2458 #define QCH_CON_LHS_ACEL_D_HSI2_QCH 0x3024
2459 #define QCH_CON_MMC_CARD_QCH 0x3028
2460 #define QCH_CON_PCIE_GEN4_1_QCH_APB_1 0x302c
2461 #define QCH_CON_PCIE_GEN4_1_QCH_APB_2 0x3030
2462 #define QCH_CON_PCIE_GEN4_1_QCH_AXI_1 0x3034
2463 #define QCH_CON_PCIE_GEN4_1_QCH_AXI_2 0x3038
2464 #define QCH_CON_PCIE_GEN4_1_QCH_DBG_1 0x303c
2465 #define QCH_CON_PCIE_GEN4_1_QCH_DBG_2 0x3040
2466 #define QCH_CON_PCIE_GEN4_1_QCH_PCS_APB 0x3044
2467 #define QCH_CON_PCIE_GEN4_1_QCH_PMA_APB 0x3048
2468 #define QCH_CON_PCIE_GEN4_1_QCH_UDBG 0x304c
2469 #define QCH_CON_PCIE_IA_GEN4A_1_QCH 0x3050
2470 #define QCH_CON_PCIE_IA_GEN4B_1_QCH 0x3054
2471 #define QCH_CON_PPMU_HSI2_QCH 0x3058
2472 #define QCH_CON_QE_MMC_CARD_HSI2_QCH 0x305c
2473 #define QCH_CON_QE_PCIE_GEN4A_HSI2_QCH 0x3060
2474 #define QCH_CON_QE_PCIE_GEN4B_HSI2_QCH 0x3064
2475 #define QCH_CON_QE_UFS_EMBD_HSI2_QCH 0x3068
2476 #define QCH_CON_SSMT_HSI2_QCH 0x306c
2477 #define QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH 0x3070
2478 #define QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH 0x3074
2479 #define QCH_CON_SYSMMU_HSI2_QCH 0x3078
2480 #define QCH_CON_SYSREG_HSI2_QCH 0x307c
2481 #define QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH 0x3080
2482 #define QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH 0x3084
2483 #define QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH 0x3088
2484 #define QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH 0x308c
2485 #define QCH_CON_UFS_EMBD_QCH 0x3090
2486 #define QCH_CON_UFS_EMBD_QCH_FMP 0x3094
2487 #define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 0x3c00
2620 21, 0, 0),
2625 21, 0, 0),
2629 21, 0, 0),
2633 21, 0, 0),
2637 21, 0, 0),
2641 21, 0, 0),
2645 21, 0, 0),
2648 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, 21, 0, 0),
2652 CLK_IGNORE_UNUSED, 0),
2657 21, CLK_IS_CRITICAL, 0),
2662 21, CLK_IS_CRITICAL, 0),
2667 21, CLK_IGNORE_UNUSED, 0),
2671 21, 0, 0),
2675 21, 0, 0),
2679 21, 0, 0),
2684 21, 0, 0),
2688 21, 0, 0),
2693 21, 0, 0),
2697 21, 0, 0),
2702 21, 0, 0),
2706 21, 0, 0),
2711 21, 0, 0),
2716 21, 0, 0),
2721 21, 0, 0),
2726 21, 0, 0),
2730 21, 0, 0),
2734 21, 0, 0),
2738 21, 0, 0),
2742 21, 0, 0),
2746 21, 0, 0),
2750 21, 0, 0),
2754 21, 0, 0),
2758 21, 0, 0),
2762 21, 0, 0),
2766 21, 0, 0),
2770 21, CLK_IS_CRITICAL, 0),
2774 21, CLK_IS_CRITICAL, 0),
2778 21, CLK_IS_CRITICAL, 0),
2782 21, 0, 0),
2787 21, CLK_IGNORE_UNUSED, 0),
2792 21, CLK_IGNORE_UNUSED, 0),
2797 21, CLK_IGNORE_UNUSED, 0),
2801 21, CLK_IS_CRITICAL, 0),
2805 21, 0, 0),
2809 21, 0, 0),
2813 21, 0, 0),
2817 21, 0, 0),
2821 21, 0, 0),
2825 21, 0, 0),
2829 21, 0, 0),
2833 21, 0, 0),
2837 21, CLK_IS_CRITICAL, 0),
2841 21, CLK_IS_CRITICAL, 0),
2845 21, CLK_IS_CRITICAL, 0),
2850 21, CLK_IGNORE_UNUSED, 0),
2855 21, CLK_IGNORE_UNUSED, 0),
2871 /* Register Offset definitions for CMU_MISC (0x10010000) */
2872 #define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600
2873 #define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604
2874 #define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610
2875 #define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614
2876 #define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800
2877 #define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810
2878 #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
2879 #define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800
2880 #define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804
2881 #define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000
2882 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004
2883 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008
2884 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c
2885 #define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010
2886 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014
2887 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018
2888 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c
2889 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020
2890 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024
2891 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028
2892 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c
2893 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030
2894 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034
2895 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038
2896 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c
2897 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040
2898 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044
2899 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048
2900 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c
2901 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050
2902 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054
2903 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058
2904 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c
2905 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060
2906 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064
2907 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068
2908 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c
2909 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070
2910 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074
2911 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078
2912 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c
2913 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080
2914 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084
2915 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088
2916 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c
2917 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090
2918 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094
2919 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098
2920 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c
2921 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0
2922 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4
2923 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8
2924 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac
2925 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0
2926 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4
2927 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8
2928 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc
2929 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0
2930 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4
2931 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8
2932 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc
2933 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0
2934 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4
2935 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8
2936 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc
2937 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0
2938 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4
2939 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8
2940 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec
2941 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0
2942 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4
2943 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8
2944 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc
2945 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100
2946 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104
2947 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108
2948 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c
2949 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110
2950 #define DMYQCH_CON_PPMU_DMA_QCH 0x3000
2951 #define DMYQCH_CON_PUF_QCH 0x3004
2952 #define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c
2953 #define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010
2954 #define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014
2955 #define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018
2956 #define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c
2957 #define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020
2958 #define QCH_CON_ADM_AHB_SSS_QCH 0x3024
2959 #define QCH_CON_DIT_QCH 0x3028
2960 #define QCH_CON_GIC_QCH 0x3030
2961 #define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038
2962 #define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c
2963 #define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040
2964 #define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044
2965 #define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048
2966 #define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c
2967 #define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050
2968 #define QCH_CON_MCT_QCH 0x3054
2969 #define QCH_CON_MISC_CMU_MISC_QCH 0x3058
2970 #define QCH_CON_OTP_CON_BIRA_QCH 0x305c
2971 #define QCH_CON_OTP_CON_BISR_QCH 0x3060
2972 #define QCH_CON_OTP_CON_TOP_QCH 0x3064
2973 #define QCH_CON_PDMA_QCH 0x3068
2974 #define QCH_CON_PPMU_MISC_QCH 0x306c
2975 #define QCH_CON_QE_DIT_QCH 0x3070
2976 #define QCH_CON_QE_PDMA_QCH 0x3074
2977 #define QCH_CON_QE_PPMU_DMA_QCH 0x3078
2978 #define QCH_CON_QE_RTIC_QCH 0x307c
2979 #define QCH_CON_QE_SPDMA_QCH 0x3080
2980 #define QCH_CON_QE_SSS_QCH 0x3084
2981 #define QCH_CON_RTIC_QCH 0x3088
2982 #define QCH_CON_SPDMA_QCH 0x308c
2983 #define QCH_CON_SSMT_DIT_QCH 0x3090
2984 #define QCH_CON_SSMT_PDMA_QCH 0x3094
2985 #define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098
2986 #define QCH_CON_SSMT_RTIC_QCH 0x309c
2987 #define QCH_CON_SSMT_SPDMA_QCH 0x30a0
2988 #define QCH_CON_SSMT_SSS_QCH 0x30a4
2989 #define QCH_CON_SSS_QCH 0x30a8
2990 #define QCH_CON_SYSMMU_MISC_QCH 0x30ac
2991 #define QCH_CON_SYSMMU_SSS_QCH 0x30b0
2992 #define QCH_CON_SYSREG_MISC_QCH 0x30b4
2993 #define QCH_CON_TMU_SUB_QCH 0x30b8
2994 #define QCH_CON_TMU_TOP_QCH 0x30bc
2995 #define QCH_CON_WDT_CLUSTER0_QCH 0x30c0
2996 #define QCH_CON_WDT_CLUSTER1_QCH 0x30c4
2997 #define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00
3139 CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 0),
3144 CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3),
3146 CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3),
3153 21, 0, 0),
3157 21, 0, 0),
3161 21, 0, 0),
3165 21, 0, 0),
3169 21, 0, 0),
3173 21, 0, 0),
3177 21, 0, 0),
3181 21, 0, 0),
3185 21, 0, 0),
3189 21, 0, 0),
3193 21, 0, 0),
3197 21, 0, 0),
3201 21, 0, 0),
3205 21, 0, 0),
3209 21, 0, 0),
3213 21, 0, 0),
3217 21, 0, 0),
3221 21, 0, 0),
3225 21, 0, 0),
3229 21, 0, 0),
3233 21, 0, 0),
3237 21, 0, 0),
3241 21, 0, 0),
3245 21, 0, 0),
3249 21, 0, 0),
3253 21, 0, 0),
3257 21, 0, 0),
3261 21, 0, 0),
3265 21, 0, 0),
3269 21, 0, 0),
3273 21, 0, 0),
3277 21, 0, 0),
3281 21, 0, 0),
3285 21, 0, 0),
3289 21, 0, 0),
3293 21, 0, 0),
3297 21, 0, 0),
3301 21, 0, 0),
3305 21, 0, 0),
3309 21, 0, 0),
3313 21, 0, 0),
3317 21, 0, 0),
3321 21, 0, 0),
3325 21, 0, 0),
3329 21, 0, 0),
3333 21, 0, 0),
3337 21, 0, 0),
3341 21, 0, 0),
3345 21, 0, 0),
3349 21, 0, 0),
3353 21, 0, 0),
3357 21, 0, 0),
3361 21, 0, 0),
3365 21, 0, 0),
3369 21, 0, 0),
3373 21, 0, 0),
3377 21, 0, 0),
3381 21, 0, 0),
3385 21, 0, 0),
3389 21, 0, 0),
3393 21, 0, 0),
3397 21, 0, 0),
3401 21, 0, 0),
3405 21, 0, 0),
3409 21, 0, 0),
3413 21, 0, 0),
3440 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */
3441 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
3442 #define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604
3443 #define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610
3444 #define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614
3445 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620
3446 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624
3447 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640
3448 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644
3449 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650
3450 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654
3451 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660
3452 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664
3453 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670
3454 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674
3455 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680
3456 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684
3457 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690
3458 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694
3459 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0
3460 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4
3461 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0
3462 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4
3463 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0
3464 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4
3465 #define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800
3466 #define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810
3467 #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800
3468 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804
3469 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c
3470 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810
3471 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814
3472 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820
3473 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824
3474 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828
3475 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c
3476 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830
3477 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834
3478 #define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000
3479 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004
3480 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008
3481 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c
3482 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010
3483 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014
3484 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018
3485 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c
3486 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020
3487 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024
3488 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028
3489 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c
3490 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030
3491 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034
3492 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038
3493 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c
3494 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040
3495 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044
3496 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048
3497 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c
3498 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050
3499 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054
3500 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058
3501 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c
3502 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060
3503 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064
3504 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068
3505 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c
3506 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070
3507 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074
3508 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078
3509 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c
3510 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080
3511 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084
3512 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088
3513 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c
3514 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090
3515 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094
3516 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098
3517 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c
3518 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4
3519 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8
3520 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0
3521 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4
3522 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8
3523 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc
3524 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4
3525 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8
3526 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc
3527 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0
3528 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4
3529 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8
3530 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc
3531 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0
3532 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4
3533 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8
3534 #define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000
3535 #define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004
3536 #define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008
3537 #define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c
3538 #define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010
3539 #define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014
3540 #define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018
3541 #define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c
3542 #define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020
3543 #define QCH_CON_D_TZPC_PERIC0_QCH 0x3024
3544 #define QCH_CON_GPC_PERIC0_QCH 0x3028
3545 #define QCH_CON_GPIO_PERIC0_QCH 0x302c
3546 #define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030
3547 #define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034
3548 #define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038
3549 #define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c
3550 #define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040
3551 #define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044
3552 #define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048
3553 #define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c
3554 #define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050
3555 #define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054
3556 #define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058
3557 #define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c
3558 #define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060
3559 #define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064
3560 #define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068
3561 #define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c
3562 #define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070
3563 #define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074
3564 #define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078
3565 #define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c
3566 #define QCH_CON_SYSREG_PERIC0_QCH 0x3080
3567 #define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00
3744 CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4),
3747 CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4),
3750 CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4,
3751 CLK_SET_RATE_PARENT, 0),
3754 CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4,
3755 CLK_SET_RATE_PARENT, 0),
3758 CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4,
3759 CLK_SET_RATE_PARENT, 0),
3762 CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4,
3763 CLK_SET_RATE_PARENT, 0),
3766 CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4,
3767 CLK_SET_RATE_PARENT, 0),
3770 CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4,
3771 CLK_SET_RATE_PARENT, 0),
3774 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4,
3775 CLK_SET_RATE_PARENT, 0),
3778 CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4,
3779 CLK_SET_RATE_PARENT, 0),
3782 CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4,
3783 CLK_SET_RATE_PARENT, 0),
3791 21, CLK_IS_CRITICAL, 0),
3795 21, 0, 0),
3799 21, 0, 0),
3803 21, 0, 0),
3807 21, CLK_IGNORE_UNUSED, 0),
3812 21, CLK_IS_CRITICAL, 0),
3816 21, CLK_SET_RATE_PARENT, 0),
3820 21, CLK_SET_RATE_PARENT, 0),
3824 21, 0, 0),
3828 21, 0, 0),
3832 21, 0, 0),
3836 21, 0, 0),
3840 21, 0, 0),
3844 21, 0, 0),
3848 21, CLK_SET_RATE_PARENT, 0),
3852 21, CLK_SET_RATE_PARENT, 0),
3856 21, CLK_SET_RATE_PARENT, 0),
3860 21, CLK_SET_RATE_PARENT, 0),
3864 21, CLK_SET_RATE_PARENT, 0),
3868 21, CLK_SET_RATE_PARENT, 0),
3872 21, 0, 0),
3876 21, 0, 0),
3880 21, 0, 0),
3884 21, 0, 0),
3888 21, 0, 0),
3892 21, 0, 0),
3896 21, 0, 0),
3900 21, 0, 0),
3904 21, 0, 0),
3908 21, 0, 0),
3912 21, 0, 0),
3916 21, 0, 0),
3920 21, 0, 0),
3924 21, 0, 0),
3928 21, 0, 0),
3932 21, 0, 0),
3936 21, 0, 0),
3940 21, 0, 0),
3945 21, CLK_IS_CRITICAL, 0),
3949 21, CLK_SET_RATE_PARENT, 0),
3954 21, CLK_IS_CRITICAL, 0),
3958 21, 0, 0),
3962 21, 0, 0),
3966 21, 0, 0),
3970 21, 0, 0),
3974 21, 0, 0),
3978 21, 0, 0),
3982 21, 0, 0),
3986 21, 0, 0),
3990 21, 0, 0),
3994 21, 0, 0),
3998 21, 0, 0),
4002 21, 0, 0),
4006 21, 0, 0),
4010 21, 0, 0),
4028 /* Register Offset definitions for CMU_PERIC1 (0x10c00000) */
4029 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
4030 #define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604
4031 #define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER 0x0610
4032 #define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER 0x0614
4033 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0620
4034 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0624
4035 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0630
4036 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0634
4037 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0640
4038 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0644
4039 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0650
4040 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0654
4041 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0660
4042 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0664
4043 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0670
4044 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0674
4045 #define PERIC1_CMU_PERIC1_CONTROLLER_OPTION 0x0800
4046 #define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 0x0810
4047 #define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
4048 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI 0x1804
4049 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
4050 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
4051 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
4052 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
4053 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI 0x1818
4054 #define CLK_CON_BUF_CLKBUF_PERIC1_IP 0x2000
4055 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004
4056 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK 0x2008
4057 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x200c
4058 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2010
4059 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK 0x2014
4060 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018
4061 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x201c
4062 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2020
4063 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
4064 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
4065 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
4066 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
4067 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
4068 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x2038
4069 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x203c
4070 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2040
4071 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2044
4072 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2048
4073 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x204c
4074 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2050
4075 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2054
4076 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2058
4077 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x205c
4078 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK 0x2060
4079 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x2064
4080 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x2068
4081 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x206c
4082 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK 0x2070
4083 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK 0x2074
4084 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078
4085 #define DMYQCH_CON_PERIC1_TOP0_QCH_S 0x3000
4086 #define PCH_CON_LHM_AXI_P_PERIC1_PCH 0x3004
4087 #define QCH_CON_D_TZPC_PERIC1_QCH 0x3008
4088 #define QCH_CON_GPC_PERIC1_QCH 0x300c
4089 #define QCH_CON_GPIO_PERIC1_QCH 0x3010
4090 #define QCH_CON_LHM_AXI_P_PERIC1_QCH 0x3014
4091 #define QCH_CON_PERIC1_CMU_PERIC1_QCH 0x3018
4092 #define QCH_CON_PERIC1_TOP0_QCH_I3C0 0x301c
4093 #define QCH_CON_PERIC1_TOP0_QCH_PWM 0x3020
4094 #define QCH_CON_PERIC1_TOP0_QCH_USI0_USI 0x3024
4095 #define QCH_CON_PERIC1_TOP0_QCH_USI10_USI 0x3028
4096 #define QCH_CON_PERIC1_TOP0_QCH_USI11_USI 0x302c
4097 #define QCH_CON_PERIC1_TOP0_QCH_USI12_USI 0x3030
4098 #define QCH_CON_PERIC1_TOP0_QCH_USI13_USI 0x3034
4099 #define QCH_CON_PERIC1_TOP0_QCH_USI9_USI 0x3038
4100 #define QCH_CON_SYSREG_PERIC1_QCH 0x303c
4101 #define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 0x3c00
4211 CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
4214 CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4,
4215 CLK_SET_RATE_PARENT, 0),
4218 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4,
4219 CLK_SET_RATE_PARENT, 0),
4222 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4,
4223 CLK_SET_RATE_PARENT, 0),
4226 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4,
4227 CLK_SET_RATE_PARENT, 0),
4230 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4,
4231 CLK_SET_RATE_PARENT, 0),
4234 CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4,
4235 CLK_SET_RATE_PARENT, 0),
4242 21, CLK_IS_CRITICAL, 0),
4246 21, 0, 0),
4250 21, 0, 0),
4254 21, 0, 0),
4258 21, 0, 0),
4262 21, CLK_IGNORE_UNUSED, 0),
4266 21, CLK_IS_CRITICAL, 0),
4270 21, CLK_SET_RATE_PARENT, 0),
4274 21, CLK_SET_RATE_PARENT, 0),
4278 21, CLK_SET_RATE_PARENT, 0),
4282 21, CLK_SET_RATE_PARENT, 0),
4286 21, CLK_SET_RATE_PARENT, 0),
4290 21, CLK_SET_RATE_PARENT, 0),
4294 21, 0, 0),
4298 21, 0, 0),
4302 21, 0, 0),
4306 21, 0, 0),
4310 21, 0, 0),
4314 21, 0, 0),
4318 21, 0, 0),
4322 21, 0, 0),
4326 21, 0, 0),
4330 21, 0, 0),
4334 21, 0, 0),
4338 21, 0, 0),
4342 21, 0, 0),
4346 21, 0, 0),
4350 21, 0, 0),
4354 21, 0, 0),
4358 21, 0, 0),
4384 return 0; in gs101_cmu_probe()