Lines Matching +full:11 +full:- +full:7
1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
31 RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM
44 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11),
51 RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM
61 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7),
65 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11),
69 RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7),
79 RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
80 RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3),
81 RK3588_CRU_RESET_OFFSET(SRST_H_I2S0_8CH, 7, 4),
82 RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 7, 7),
83 RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10),
84 RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11),
85 RK3588_CRU_RESET_OFFSET(SRST_H_I2S2_2CH, 7, 12),
86 RK3588_CRU_RESET_OFFSET(SRST_H_I2S3_2CH, 7, 13),
99 RK3588_CRU_RESET_OFFSET(SRST_PDM1, 9, 7),
108 RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7),
112 RK3588_CRU_RESET_OFFSET(SRST_P_I2C4, 10, 11),
119 RK3588_CRU_RESET_OFFSET(SRST_I2C1, 11, 0),
120 RK3588_CRU_RESET_OFFSET(SRST_I2C2, 11, 1),
121 RK3588_CRU_RESET_OFFSET(SRST_I2C3, 11, 2),
122 RK3588_CRU_RESET_OFFSET(SRST_I2C4, 11, 3),
123 RK3588_CRU_RESET_OFFSET(SRST_I2C5, 11, 4),
124 RK3588_CRU_RESET_OFFSET(SRST_I2C6, 11, 5),
125 RK3588_CRU_RESET_OFFSET(SRST_I2C7, 11, 6),
126 RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7),
127 RK3588_CRU_RESET_OFFSET(SRST_P_CAN0, 11, 8),
128 RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9),
129 RK3588_CRU_RESET_OFFSET(SRST_P_CAN1, 11, 10),
130 RK3588_CRU_RESET_OFFSET(SRST_CAN1, 11, 11),
131 RK3588_CRU_RESET_OFFSET(SRST_P_CAN2, 11, 12),
132 RK3588_CRU_RESET_OFFSET(SRST_CAN2, 11, 13),
133 RK3588_CRU_RESET_OFFSET(SRST_P_SARADC, 11, 14),
143 RK3588_CRU_RESET_OFFSET(SRST_P_UART6, 12, 7),
161 RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7),
165 RK3588_CRU_RESET_OFFSET(SRST_SPI0, 14, 11),
178 RK3588_CRU_RESET_OFFSET(SRST_PWM2, 15, 7),
193 RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER8, 16, 7),
197 RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 16, 11),
211 RK3588_CRU_RESET_OFFSET(SRST_P_DECOM, 17, 7),
214 RK3588_CRU_RESET_OFFSET(SRST_A_GICADB_GIC2CORE_BUS, 17, 11),
230 RK3588_CRU_RESET_OFFSET(SRST_OTPC_ARB, 18, 11),
245 RK3588_CRU_RESET_OFFSET(SRST_SBR_CH0, 20, 7),
249 RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH0, 20, 11),
263 RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH1, 21, 7),
277 RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 22, 7),
288 RK3588_CRU_RESET_OFFSET(SRST_SBR_CH2, 23, 7),
292 RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH2, 23, 11),
306 RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH3, 24, 7),
320 RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH2, 25, 7),
348 RK3588_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 29, 11),
359 RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 30, 7),
369 RK3588_CRU_RESET_OFFSET(SRST_B_EMMC, 31, 7),
373 RK3588_CRU_RESET_OFFSET(SRST_H_SFC_XIP, 31, 11),
382 RK3588_CRU_RESET_OFFSET(SRST_A_GMAC1, 32, 11),
399 RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PCIE, 34, 7),
404 RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG2, 35, 7),
410 RK3588_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 7),
414 RK3588_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 11),
426 RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CA, 40, 7),
436 RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_HEVC_CA, 41, 7),
443 RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 42, 7),
445 RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB0, 42, 11),
460 RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER_BIU, 44, 7),
464 RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER0, 44, 11),
478 RK3588_CRU_RESET_OFFSET(SRST_H_RGA2, 45, 7),
482 RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_0, 45, 11),
504 RK3588_CRU_RESET_OFFSET(SRST_A_VICAP, 49, 7),
507 RK3588_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 49, 11),
515 RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 50, 7),
523 RK3588_CRU_RESET_OFFSET(SRST_CSIHOST3_VICAP, 51, 7),
532 RK3588_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 52, 7),
547 RK3588_CRU_RESET_OFFSET(SRST_DSIHOST1, 53, 7),
554 RK3588_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 55, 7),
558 RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY0, 55, 11),
575 RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF5_DP1, 57, 7),
576 RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF5_DP1, 57, 11),
580 RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX_BIU, 59, 7),
584 RK3588_CRU_RESET_OFFSET(SRST_P_VOP1_BIU, 59, 11),
596 RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX0, 60, 11),
601 RK3588_CRU_RESET_OFFSET(SRST_HDMITX1_REF, 61, 7),
604 RK3588_CRU_RESET_OFFSET(SRST_HDMIRX_REF, 61, 11),
619 RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF3, 63, 7),
621 RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF4, 63, 11),
639 RK3588_CRU_RESET_OFFSET(SRST_M_I2S10_8CH_RX, 65, 7),
648 RK3588_CRU_RESET_OFFSET(SRST_A_M2_GPU_BIU, 66, 11),
669 RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 69, 7),
671 RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S400_BIU, 69, 11),
683 RK3588_CRU_RESET_OFFSET(SRST_P_WDT, 70, 7),
687 RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 70, 11),
697 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_BOT_RIGHT, 72, 7),
701 RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_1_GRF0, 72, 11),
715 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1, 73, 7), // missing in TRM
740 RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY1, 77, 7),
750 RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY2, 0, 7),
757 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11),
768 RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 1, 7),
771 RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER1, 1, 11),
780 RK3588_PMU1CRU_RESET_OFFSET(SRST_H_I2S1_8CH, 2, 7),
788 RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_INIT, 3, 11),
800 RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_0, 4, 7),
813 RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11),
826 RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11),