Lines Matching +full:10 +full:- +full:11
1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
43 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LANE, 2, 10),
44 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11),
51 RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM
64 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_TOP, 4, 10),
65 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11),
83 RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10),
84 RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11),
102 RK3588_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 10, 1),
103 RK3588_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 10, 2),
104 RK3588_CRU_RESET_OFFSET(SRST_A_GIC, 10, 3),
105 RK3588_CRU_RESET_OFFSET(SRST_A_GIC_DBG, 10, 4),
106 RK3588_CRU_RESET_OFFSET(SRST_A_DMAC0, 10, 5),
107 RK3588_CRU_RESET_OFFSET(SRST_A_DMAC1, 10, 6),
108 RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7),
109 RK3588_CRU_RESET_OFFSET(SRST_P_I2C1, 10, 8),
110 RK3588_CRU_RESET_OFFSET(SRST_P_I2C2, 10, 9),
111 RK3588_CRU_RESET_OFFSET(SRST_P_I2C3, 10, 10),
112 RK3588_CRU_RESET_OFFSET(SRST_P_I2C4, 10, 11),
113 RK3588_CRU_RESET_OFFSET(SRST_P_I2C5, 10, 12),
114 RK3588_CRU_RESET_OFFSET(SRST_P_I2C6, 10, 13),
115 RK3588_CRU_RESET_OFFSET(SRST_P_I2C7, 10, 14),
116 RK3588_CRU_RESET_OFFSET(SRST_P_I2C8, 10, 15),
119 RK3588_CRU_RESET_OFFSET(SRST_I2C1, 11, 0),
120 RK3588_CRU_RESET_OFFSET(SRST_I2C2, 11, 1),
121 RK3588_CRU_RESET_OFFSET(SRST_I2C3, 11, 2),
122 RK3588_CRU_RESET_OFFSET(SRST_I2C4, 11, 3),
123 RK3588_CRU_RESET_OFFSET(SRST_I2C5, 11, 4),
124 RK3588_CRU_RESET_OFFSET(SRST_I2C6, 11, 5),
125 RK3588_CRU_RESET_OFFSET(SRST_I2C7, 11, 6),
126 RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7),
127 RK3588_CRU_RESET_OFFSET(SRST_P_CAN0, 11, 8),
128 RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9),
129 RK3588_CRU_RESET_OFFSET(SRST_P_CAN1, 11, 10),
130 RK3588_CRU_RESET_OFFSET(SRST_CAN1, 11, 11),
131 RK3588_CRU_RESET_OFFSET(SRST_P_CAN2, 11, 12),
132 RK3588_CRU_RESET_OFFSET(SRST_CAN2, 11, 13),
133 RK3588_CRU_RESET_OFFSET(SRST_P_SARADC, 11, 14),
146 RK3588_CRU_RESET_OFFSET(SRST_P_UART9, 12, 10),
164 RK3588_CRU_RESET_OFFSET(SRST_P_SPI4, 14, 10),
165 RK3588_CRU_RESET_OFFSET(SRST_SPI0, 14, 11),
180 RK3588_CRU_RESET_OFFSET(SRST_PWM3, 15, 10),
196 RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER11, 16, 10),
197 RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 16, 11),
214 RK3588_CRU_RESET_OFFSET(SRST_A_GICADB_GIC2CORE_BUS, 17, 11),
229 RK3588_CRU_RESET_OFFSET(SRST_OTPC_NS, 18, 10),
230 RK3588_CRU_RESET_OFFSET(SRST_OTPC_ARB, 18, 11),
248 RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 20, 10),
249 RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH0, 20, 11),
291 RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH2, 23, 10),
292 RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH2, 23, 11),
347 RK3588_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 29, 10),
348 RK3588_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 29, 11),
372 RK3588_CRU_RESET_OFFSET(SRST_H_SFC, 31, 10),
373 RK3588_CRU_RESET_OFFSET(SRST_H_SFC_XIP, 31, 11),
381 RK3588_CRU_RESET_OFFSET(SRST_A_GMAC0, 32, 10),
382 RK3588_CRU_RESET_OFFSET(SRST_A_GMAC1, 32, 11),
413 RK3588_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 10),
414 RK3588_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 11),
444 RK3588_CRU_RESET_OFFSET(SRST_H_HOST0, 42, 10),
445 RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB0, 42, 11),
463 RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER0, 44, 10),
464 RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER0, 44, 11),
481 RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_0, 45, 10),
482 RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_0, 45, 11),
506 RK3588_CRU_RESET_OFFSET(SRST_ISP0, 49, 10),
507 RK3588_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 49, 11),
557 RK3588_CRU_RESET_OFFSET(SRST_P_VO0GRF, 55, 10),
558 RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY0, 55, 11),
567 RK3588_CRU_RESET_OFFSET(SRST_H_I2S4_8CH, 56, 10),
576 RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF5_DP1, 57, 11),
583 RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10),
584 RK3588_CRU_RESET_OFFSET(SRST_P_VOP1_BIU, 59, 11),
595 RK3588_CRU_RESET_OFFSET(SRST_P_TRNG1, 60, 10),
596 RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX0, 60, 11),
603 RK3588_CRU_RESET_OFFSET(SRST_P_HDMIRX, 61, 10),
604 RK3588_CRU_RESET_OFFSET(SRST_HDMIRX_REF, 61, 11),
621 RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF4, 63, 11),
647 RK3588_CRU_RESET_OFFSET(SRST_A_M1_GPU_BIU, 66, 10),
648 RK3588_CRU_RESET_OFFSET(SRST_A_M2_GPU_BIU, 66, 11),
670 RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S200_BIU, 69, 10),
671 RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S400_BIU, 69, 11),
686 RK3588_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 70, 10),
687 RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 70, 11),
700 RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_0_GRF0, 72, 10),
701 RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_1_GRF0, 72, 11),
718 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS_HS, 73, 10), // missing in TRM
753 RK3588_PHPTOPCRU_RESET_OFFSET(SRST_PCIE30_PHY, 0, 10),
756 RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 10),
757 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11),
770 RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER0, 1, 10),
771 RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER1, 1, 11),
781 RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_TX, 2, 10),
788 RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_INIT, 3, 11),
803 RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_1, 4, 10),
812 RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10),
813 RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11),
825 RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10),
826 RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11),