Lines Matching full:xin24m
278 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
279 PNAME(mux_24m_32k_p) = { "xin24m", "xin_osc0_div" };
280 PNAME(mux_armclkl_p) = { "xin24m", "pll_lpll", "lpll" };
281 PNAME(mux_armclkb_p) = { "xin24m", "pll_bpll", "bpll" };
282 PNAME(gpll_24m_p) = { "gpll", "xin24m" };
283 PNAME(cpll_24m_p) = { "cpll", "xin24m" };
287 PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" };
288 PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };
289 PNAME(gpll_cpll_aupll_24m_p) = { "gpll", "cpll", "aupll", "xin24m" };
295 PNAME(gpll_cpll_vpll_aupll_24m_p) = { "gpll", "cpll", "vpll", "aupll", "xin24m" };
302 PNAME(gpll_cpll_spll_aupll_lpll_24m_p) = { "gpll", "cpll", "spll", "aupll", "lpll_dummy", "xin24m" …
305 PNAME(mux_24m_ccipvtpll_gpll_lpll_p) = { "xin24m", "cci_pvtpll", "gpll", "lpll" };
306 PNAME(mux_24m_spll_gpll_cpll_p) = {"xin24m", "spll", "gpll", "cpll" };
307 PNAME(audio_frac_int_p) = { "xin24m", "clk_audio_frac_0", "clk_audio_frac_1", "clk_audio_frac_2",
310 PNAME(mux_100m_24m_p) = { "clk_cpll_div10", "xin24m" };
311 PNAME(mux_100m_50m_24m_p) = { "clk_cpll_div10", "clk_cpll_div20", "xin24m" };
312 PNAME(mux_100m_24m_lclk0_p) = { "clk_cpll_div10", "xin24m", "lclk_asrc_src_0" };
313 PNAME(mux_100m_24m_lclk1_p) = { "clk_cpll_div10", "xin24m", "lclk_asrc_src_1" };
314 PNAME(mux_150m_100m_50m_24m_p) = { "clk_gpll_div8", "clk_cpll_div10", "clk_cpll_div20", "xin24m" };
315 PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_cpll_div10", "clk_cpll_div20", "xin24m" };
316 PNAME(mux_400m_200m_100m_24m_p) = { "clk_gpll_div3", "clk_gpll_div6", "clk_cpll_div10", "xin24m" };
317 PNAME(mux_500m_250m_100m_24m_p) = { "clk_cpll_div2", "clk_cpll_div4", "clk_cpll_div10", "xin24m" };
318 PNAME(mux_600m_400m_300m_24m_p) = { "clk_gpll_div2", "clk_gpll_div3", "clk_gpll_div4", "xin24m" };
319 PNAME(mux_350m_175m_116m_24m_p) = { "clk_spll_div2", "clk_spll_div4", "clk_spll_div6", "xin24m" };
320 PNAME(mux_175m_116m_58m_24m_p) = { "clk_spll_div4", "clk_spll_div6", "clk_spll_div12", "xin24m" };
321 PNAME(mux_116m_58m_24m_p) = { "clk_spll_div6", "clk_spll_div12", "xin24m" };
332 PNAME(uart1_p) = { "clk_uart1_src_top", "xin24m" };
336 "dclk_ebc_frac", "xin24m" };
340 PNAME(clk_uart_p) = { "gpll", "cpll", "aupll", "xin24m", "clk_uart_frac_0",
349 "xin24m"};
351 "aclk_vi_root_inter", "xin24m"};
352 PNAME(clk_ref_osc_mphy_p) = { "xin24m", "clk_gpio_mphy_i", "clk_ref_mphy_26m"};
354 "clk_50m_pmu_src", "xin24m" };
355 PNAME(mux_pmu100m_pmu50m_24m_p) = { "clk_100m_pmu_src", "clk_50m_pmu_src", "xin24m" };
356 PNAME(mux_pmu100m_24m_32k_p) = { "clk_100m_pmu_src", "xin24m", "xin_osc0_div" };
357 PNAME(clk_phy_ref_src_p) = { "xin24m", "clk_pmuphy_ref_src" };
359 PNAME(clk_cpll_ref_src_p) = { "xin24m", "clk_usbphy_ref_src" };
360 PNAME(clk_aupll_ref_src_p) = { "xin24m", "clk_aupll_ref_io" };
391 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
393 COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IS_CRITICAL,
542 GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
577 GATE(CLK_KEY_SHIFT, "clk_key_shift", "xin24m", CLK_IS_CRITICAL,
599 GATE(TCLK_WDT_BUSMCU, "tclk_wdt_busmcu", "xin24m", 0,
637 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
722 GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0,
729 GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0,
756 GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
760 GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
764 GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
768 GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
821 GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0,
895 GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0,
940 GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0,
977 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
992 GATE(CLK_REF_USB3OTG0, "clk_ref_usb3otg0", "xin24m", 0,
994 GATE(CLK_SUSPEND_USB3OTG0, "clk_suspend_usb3otg0", "xin24m", 0,
1152 GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0,
1327 GATE(CLK_PCIE0_AUX, "clk_pcie0_aux", "xin24m", 0,
1337 GATE(CLK_REF_USB3OTG1, "clk_ref_usb3otg1", "xin24m", 0,
1339 GATE(CLK_SUSPEND_USB3OTG1, "clk_suspend_usb3otg1", "xin24m", 0,
1351 GATE(CLK_PCIE1_AUX, "clk_pcie1_aux", "xin24m", 0,
1365 GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", CLK_IS_CRITICAL,
1367 GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", CLK_IS_CRITICAL,
1593 GATE(CLK_PMU1, "clk_pmu1", "xin24m", CLK_IS_CRITICAL,
1608 GATE(CLK_USBDP_COMBO_PHY_IMMORTAL, "clk_usbdp_combo_phy_immortal", "xin24m", 0,
1610 GATE(CLK_HDMITXHDP, "clk_hdmitxhdp", "xin24m", 0,
1642 GATE(CLK_PMU1PWM_OSC, "clk_pmu1pwm_osc", "xin24m", 0,
1672 GATE(CLK_OSC0_PMU1, "clk_osc0_pmu1", "xin24m", CLK_IS_CRITICAL,
1701 GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0,