946 struct pll_clk {  struct
955 #define to_pll(_hw)	container_of(_hw, struct pll_clk, hw)  argument
960 	struct pll_clk *pll_clk = to_pll(hw);  in rzg2l_cpg_pll_clk_recalc_rate()  local
961 	struct rzg2l_cpg_priv *priv = pll_clk->priv;  in rzg2l_cpg_pll_clk_recalc_rate()
965 	if (pll_clk->type != CLK_TYPE_SAM_PLL)  in rzg2l_cpg_pll_clk_recalc_rate()
968 	val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));  in rzg2l_cpg_pll_clk_recalc_rate()
969 	val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));  in rzg2l_cpg_pll_clk_recalc_rate()
984 	struct pll_clk *pll_clk = to_pll(hw);  in rzg3s_cpg_pll_clk_recalc_rate()  local
985 	struct rzg2l_cpg_priv *priv = pll_clk->priv;  in rzg3s_cpg_pll_clk_recalc_rate()
989 	if (pll_clk->type != CLK_TYPE_G3S_PLL)  in rzg3s_cpg_pll_clk_recalc_rate()
992 	setting = GET_REG_SAMPLL_SETTING(pll_clk->conf);  in rzg3s_cpg_pll_clk_recalc_rate()
996 			return pll_clk->default_rate;  in rzg3s_cpg_pll_clk_recalc_rate()
999 	val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));  in rzg3s_cpg_pll_clk_recalc_rate()
1028 	struct pll_clk *pll_clk;  in rzg2l_cpg_pll_clk_register()  local
1035 	pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);  in rzg2l_cpg_pll_clk_register()
1036 	if (!pll_clk)  in rzg2l_cpg_pll_clk_register()
1046 	pll_clk->hw.init = &init;  in rzg2l_cpg_pll_clk_register()
1047 	pll_clk->conf = core->conf;  in rzg2l_cpg_pll_clk_register()
1048 	pll_clk->base = priv->base;  in rzg2l_cpg_pll_clk_register()
1049 	pll_clk->priv = priv;  in rzg2l_cpg_pll_clk_register()
1050 	pll_clk->type = core->type;  in rzg2l_cpg_pll_clk_register()
1051 	pll_clk->default_rate = core->default_rate;  in rzg2l_cpg_pll_clk_register()
1053 	ret = devm_clk_hw_register(dev, &pll_clk->hw);  in rzg2l_cpg_pll_clk_register()
1057 	return pll_clk->hw.clk;  in rzg2l_cpg_pll_clk_register()