42 #define GET_SHIFT(val)		((val >> 12) & 0xff)  argument
43 #define GET_WIDTH(val)		((val >> 8) & 0xf)  argument
45 #define KDIV(val)		((s16)FIELD_GET(GENMASK(31, 16), val))  argument
46 #define MDIV(val)		FIELD_GET(GENMASK(15, 6), val)  argument
47 #define PDIV(val)		FIELD_GET(GENMASK(5, 0), val)  argument
48 #define SDIV(val)		FIELD_GET(GENMASK(2, 0), val)  argument
61 #define GET_REG_OFFSET(val)		((val >> 20) & 0xfff)  argument
62 #define GET_REG_SAMPLL_CLK1(val)	((val >> 22) & 0xfff)  argument
63 #define GET_REG_SAMPLL_CLK2(val)	((val >> 12) & 0xfff)  argument
64 #define GET_REG_SAMPLL_SETTING(val)	((val) & 0xfff)  argument
173 	u32 val;  in rzg2l_cpg_wait_clk_update_done()  local
233 	u32 val;  in rzg3s_cpg_div_clk_notifier()  local
291 	u32 val;  in rzg3s_div_clk_recalc_rate()  local
322 	u32 val;  in rzg3s_div_clk_set_rate()  local
347 	struct clk_init_data init = {};  in rzg3s_cpg_div_clk_register()  local
468 	u32 val;  in rzg2l_cpg_sd_clk_mux_set_parent()  local
493 	u32 val;  in rzg2l_cpg_sd_clk_mux_get_parent()  local
513 	struct clk_init_data init;  in rzg2l_cpg_sd_mux_clk_register()  local
659 	struct clk_init_data init;  in rzg2l_cpg_dsi_div_clk_register()  local
753 	struct clk_init_data init;  in rzg2l_cpg_pll5_4_mux_clk_register()  local
833 	u32 val;  in rzg2l_cpg_sipll5_set_rate()  local
904 	struct clk_init_data init;  in rzg2l_cpg_sipll5_register()  local
986 	u32 nir, nfr, mr, pr, val, setting;  in rzg3s_cpg_pll_clk_recalc_rate()  local
1026 	struct clk_init_data init;  in rzg2l_cpg_pll_clk_register()  local
1347 	struct clk_init_data init;  in rzg2l_cpg_register_mod_clk()  local