1 // SPDX-License-Identifier: GPL-2.0
3  * Renesas Clock Pulse Generator / Module Standby and Software Reset
7  * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
14 #include <linux/clk-provider.h>
28 #include <linux/reset-controller.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
45  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
46  * R-Car Gen2, R-Car Gen3, and RZ/G1.
47  * These are NOT valid for R-Car Gen1 and RZ/A1!
125  * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
129  * @dev: CPG/MSSR device
130  * @base: CPG/MSSR register block base address
131  * @reg_layout: CPG/MSSR register layout
133  * @np: Device node in DT for this CPG/MSSR module
136  * @last_dt_core_clk: ID of the last Core Clock exported to DT
137  * @notifiers: Notifier chain to save/restore clock state for system resume
181  * struct mstp_clock - MSTP gating clock
182  * @hw: handle between common and hardware-specific interfaces
183  * @index: MSTP clock number
184  * @priv: CPG/MSSR private data
196 	struct mstp_clock *clock = to_mstp_clock(hw);  in cpg_mstp_clock_endisable()  local
197 	struct cpg_mssr_priv *priv = clock->priv;  in cpg_mstp_clock_endisable()
198 	unsigned int reg = clock->index / 32;  in cpg_mstp_clock_endisable()
199 	unsigned int bit = clock->index % 32;  in cpg_mstp_clock_endisable()
200 	struct device *dev = priv->dev;  in cpg_mstp_clock_endisable()
206 	dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,  in cpg_mstp_clock_endisable()
208 	spin_lock_irqsave(&priv->rmw_lock, flags);  in cpg_mstp_clock_endisable()
210 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {  in cpg_mstp_clock_endisable()
211 		value = readb(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
216 		writeb(value, priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
219 		readb(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
220 		barrier_data(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
222 		value = readl(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
227 		writel(value, priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
230 	spin_unlock_irqrestore(&priv->rmw_lock, flags);  in cpg_mstp_clock_endisable()
232 	if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)  in cpg_mstp_clock_endisable()
235 	error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg],  in cpg_mstp_clock_endisable()
239 			priv->base + priv->control_regs[reg], bit);  in cpg_mstp_clock_endisable()
256 	struct mstp_clock *clock = to_mstp_clock(hw);  in cpg_mstp_clock_is_enabled()  local
257 	struct cpg_mssr_priv *priv = clock->priv;  in cpg_mstp_clock_is_enabled()
260 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)  in cpg_mstp_clock_is_enabled()
261 		value = readb(priv->base + priv->control_regs[clock->index / 32]);  in cpg_mstp_clock_is_enabled()
263 		value = readl(priv->base + priv->status_regs[clock->index / 32]);  in cpg_mstp_clock_is_enabled()
265 	return !(value & BIT(clock->index % 32));  in cpg_mstp_clock_is_enabled()
278 	unsigned int clkidx = clkspec->args[1];  in cpg_mssr_clk_src_twocell_get()
280 	struct device *dev = priv->dev;  in cpg_mssr_clk_src_twocell_get()
286 	switch (clkspec->args[0]) {  in cpg_mssr_clk_src_twocell_get()
289 		if (clkidx > priv->last_dt_core_clk) {  in cpg_mssr_clk_src_twocell_get()
290 			dev_err(dev, "Invalid %s clock index %u\n", type,  in cpg_mssr_clk_src_twocell_get()
292 			return ERR_PTR(-EINVAL);  in cpg_mssr_clk_src_twocell_get()
294 		clk = priv->clks[clkidx];  in cpg_mssr_clk_src_twocell_get()
299 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {  in cpg_mssr_clk_src_twocell_get()
301 			range_check = 7 - (clkidx % 10);  in cpg_mssr_clk_src_twocell_get()
304 			range_check = 31 - (clkidx % 100);  in cpg_mssr_clk_src_twocell_get()
306 		if (range_check < 0 || idx >= priv->num_mod_clks) {  in cpg_mssr_clk_src_twocell_get()
307 			dev_err(dev, "Invalid %s clock index %u\n", type,  in cpg_mssr_clk_src_twocell_get()
309 			return ERR_PTR(-EINVAL);  in cpg_mssr_clk_src_twocell_get()
311 		clk = priv->clks[priv->num_core_clks + idx];  in cpg_mssr_clk_src_twocell_get()
315 		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);  in cpg_mssr_clk_src_twocell_get()
316 		return ERR_PTR(-EINVAL);  in cpg_mssr_clk_src_twocell_get()
320 		dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,  in cpg_mssr_clk_src_twocell_get()
323 		dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",  in cpg_mssr_clk_src_twocell_get()
324 			clkspec->args[0], clkspec->args[1], clk,  in cpg_mssr_clk_src_twocell_get()
333 	struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;  in cpg_mssr_register_core_clk()
334 	struct device *dev = priv->dev;  in cpg_mssr_register_core_clk()
335 	unsigned int id = core->id, div = core->div;  in cpg_mssr_register_core_clk()
338 	WARN_DEBUG(id >= priv->num_core_clks);  in cpg_mssr_register_core_clk()
339 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);  in cpg_mssr_register_core_clk()
341 	if (!core->name) {  in cpg_mssr_register_core_clk()
342 		/* Skip NULLified clock */  in cpg_mssr_register_core_clk()
346 	switch (core->type) {  in cpg_mssr_register_core_clk()
348 		clk = of_clk_get_by_name(priv->np, core->name);  in cpg_mssr_register_core_clk()
354 		WARN_DEBUG(core->parent >= priv->num_core_clks);  in cpg_mssr_register_core_clk()
355 		parent = priv->clks[core->parent];  in cpg_mssr_register_core_clk()
363 		if (core->type == CLK_TYPE_DIV6_RO)  in cpg_mssr_register_core_clk()
364 			/* Multiply with the DIV6 register value */  in cpg_mssr_register_core_clk()
365 			div *= (readl(priv->base + core->offset) & 0x3f) + 1;  in cpg_mssr_register_core_clk()
367 		if (core->type == CLK_TYPE_DIV6P1) {  in cpg_mssr_register_core_clk()
368 			clk = cpg_div6_register(core->name, 1, &parent_name,  in cpg_mssr_register_core_clk()
369 						priv->base + core->offset,  in cpg_mssr_register_core_clk()
370 						&priv->notifiers);  in cpg_mssr_register_core_clk()
372 			clk = clk_register_fixed_factor(NULL, core->name,  in cpg_mssr_register_core_clk()
374 							core->mult, div);  in cpg_mssr_register_core_clk()
379 		clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,  in cpg_mssr_register_core_clk()
380 					      core->mult);  in cpg_mssr_register_core_clk()
384 		if (info->cpg_clk_register)  in cpg_mssr_register_core_clk()
385 			clk = info->cpg_clk_register(dev, core, info,  in cpg_mssr_register_core_clk()
386 						     priv->clks, priv->base,  in cpg_mssr_register_core_clk()
387 						     &priv->notifiers);  in cpg_mssr_register_core_clk()
389 			dev_err(dev, "%s has unsupported core clock type %u\n",  in cpg_mssr_register_core_clk()
390 				core->name, core->type);  in cpg_mssr_register_core_clk()
397 	dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));  in cpg_mssr_register_core_clk()
398 	priv->clks[id] = clk;  in cpg_mssr_register_core_clk()
402 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",  in cpg_mssr_register_core_clk()
403 		core->name, PTR_ERR(clk));  in cpg_mssr_register_core_clk()
410 	struct mstp_clock *clock = NULL;  in cpg_mssr_register_mod_clk()  local
411 	struct device *dev = priv->dev;  in cpg_mssr_register_mod_clk()
412 	unsigned int id = mod->id;  in cpg_mssr_register_mod_clk()
418 	WARN_DEBUG(id < priv->num_core_clks);  in cpg_mssr_register_mod_clk()
419 	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);  in cpg_mssr_register_mod_clk()
420 	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);  in cpg_mssr_register_mod_clk()
421 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);  in cpg_mssr_register_mod_clk()
423 	if (!mod->name) {  in cpg_mssr_register_mod_clk()
424 		/* Skip NULLified clock */  in cpg_mssr_register_mod_clk()
428 	parent = priv->clks[mod->parent];  in cpg_mssr_register_mod_clk()
434 	clock = kzalloc(sizeof(*clock), GFP_KERNEL);  in cpg_mssr_register_mod_clk()
435 	if (!clock) {  in cpg_mssr_register_mod_clk()
436 		clk = ERR_PTR(-ENOMEM);  in cpg_mssr_register_mod_clk()
440 	init.name = mod->name;  in cpg_mssr_register_mod_clk()
447 	clock->index = id - priv->num_core_clks;  in cpg_mssr_register_mod_clk()
448 	clock->priv = priv;  in cpg_mssr_register_mod_clk()
449 	clock->hw.init = &init;  in cpg_mssr_register_mod_clk()
451 	for (i = 0; i < info->num_crit_mod_clks; i++)  in cpg_mssr_register_mod_clk()
452 		if (id == info->crit_mod_clks[i] &&  in cpg_mssr_register_mod_clk()
453 		    cpg_mstp_clock_is_enabled(&clock->hw)) {  in cpg_mssr_register_mod_clk()
455 				mod->name);  in cpg_mssr_register_mod_clk()
465 	for (i = 0; i < priv->num_reserved_ids; i++) {  in cpg_mssr_register_mod_clk()
466 		if (id == priv->reserved_ids[i]) {  in cpg_mssr_register_mod_clk()
467 			dev_info(dev, "Ignore Linux non-assigned mod (%s)\n", mod->name);  in cpg_mssr_register_mod_clk()
473 	clk = clk_register(NULL, &clock->hw);  in cpg_mssr_register_mod_clk()
477 	dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));  in cpg_mssr_register_mod_clk()
478 	priv->clks[id] = clk;  in cpg_mssr_register_mod_clk()
479 	priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);  in cpg_mssr_register_mod_clk()
483 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",  in cpg_mssr_register_mod_clk()
484 		mod->name, PTR_ERR(clk));  in cpg_mssr_register_mod_clk()
485 	kfree(clock);  in cpg_mssr_register_mod_clk()
501 	if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)  in cpg_mssr_is_pm_clk()
504 	switch (clkspec->args[0]) {  in cpg_mssr_is_pm_clk()
506 		for (i = 0; i < pd->num_core_pm_clks; i++)  in cpg_mssr_is_pm_clk()
507 			if (clkspec->args[1] == pd->core_pm_clks[i])  in cpg_mssr_is_pm_clk()
522 	struct device_node *np = dev->of_node;  in cpg_mssr_attach_dev()
529 		dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");  in cpg_mssr_attach_dev()
530 		return -EPROBE_DEFER;  in cpg_mssr_attach_dev()
533 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,  in cpg_mssr_attach_dev()
583 	struct device_node *np = dev->of_node;  in cpg_mssr_add_clk_domain()
591 		return -ENOMEM;  in cpg_mssr_add_clk_domain()
593 	pd->num_core_pm_clks = num_core_pm_clks;  in cpg_mssr_add_clk_domain()
594 	memcpy(pd->core_pm_clks, core_pm_clks, pm_size);  in cpg_mssr_add_clk_domain()
596 	genpd = &pd->genpd;  in cpg_mssr_add_clk_domain()
597 	genpd->name = np->name;  in cpg_mssr_add_clk_domain()
598 	genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |  in cpg_mssr_add_clk_domain()
600 	genpd->attach_dev = cpg_mssr_attach_dev;  in cpg_mssr_add_clk_domain()
601 	genpd->detach_dev = cpg_mssr_detach_dev;  in cpg_mssr_add_clk_domain()
627 	dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);  in cpg_mssr_reset()
630 	writel(bitmask, priv->base + priv->reset_regs[reg]);  in cpg_mssr_reset()
632 	/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */  in cpg_mssr_reset()
636 	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);  in cpg_mssr_reset()
648 	dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);  in cpg_mssr_assert()
650 	writel(bitmask, priv->base + priv->reset_regs[reg]);  in cpg_mssr_assert()
662 	dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);  in cpg_mssr_deassert()
664 	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);  in cpg_mssr_deassert()
676 	return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);  in cpg_mssr_status()
690 	unsigned int unpacked = reset_spec->args[0];  in cpg_mssr_reset_xlate()
693 	if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {  in cpg_mssr_reset_xlate()
694 		dev_err(priv->dev, "Invalid reset index %u\n", unpacked);  in cpg_mssr_reset_xlate()
695 		return -EINVAL;  in cpg_mssr_reset_xlate()
703 	priv->rcdev.ops = &cpg_mssr_reset_ops;  in cpg_mssr_reset_controller_register()
704 	priv->rcdev.of_node = priv->dev->of_node;  in cpg_mssr_reset_controller_register()
705 	priv->rcdev.of_reset_n_cells = 1;  in cpg_mssr_reset_controller_register()
706 	priv->rcdev.of_xlate = cpg_mssr_reset_xlate;  in cpg_mssr_reset_controller_register()
707 	priv->rcdev.nr_resets = priv->num_mod_clks;  in cpg_mssr_reset_controller_register()
708 	return devm_reset_controller_register(priv->dev, &priv->rcdev);  in cpg_mssr_reset_controller_register()
721 		.compatible = "renesas,r7s9210-cpg-mssr",
727 		.compatible = "renesas,r8a7742-cpg-mssr",
733 		.compatible = "renesas,r8a7743-cpg-mssr",
738 		.compatible = "renesas,r8a7744-cpg-mssr",
744 		.compatible = "renesas,r8a7745-cpg-mssr",
750 		.compatible = "renesas,r8a77470-cpg-mssr",
756 		.compatible = "renesas,r8a774a1-cpg-mssr",
762 		.compatible = "renesas,r8a774b1-cpg-mssr",
768 		.compatible = "renesas,r8a774c0-cpg-mssr",
774 		.compatible = "renesas,r8a774e1-cpg-mssr",
780 		.compatible = "renesas,r8a7790-cpg-mssr",
786 		.compatible = "renesas,r8a7791-cpg-mssr",
789 	/* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
791 		.compatible = "renesas,r8a7793-cpg-mssr",
797 		.compatible = "renesas,r8a7792-cpg-mssr",
803 		.compatible = "renesas,r8a7794-cpg-mssr",
809 		.compatible = "renesas,r8a7795-cpg-mssr",
815 		.compatible = "renesas,r8a7796-cpg-mssr",
821 		.compatible = "renesas,r8a77961-cpg-mssr",
827 		.compatible = "renesas,r8a77965-cpg-mssr",
833 		.compatible = "renesas,r8a77970-cpg-mssr",
839 		.compatible = "renesas,r8a77980-cpg-mssr",
845 		.compatible = "renesas,r8a77990-cpg-mssr",
851 		.compatible = "renesas,r8a77995-cpg-mssr",
857 		.compatible = "renesas,r8a779a0-cpg-mssr",
863 		.compatible = "renesas,r8a779f0-cpg-mssr",
869 		.compatible = "renesas,r8a779g0-cpg-mssr",
875 		.compatible = "renesas,r8a779h0-cpg-mssr",
898 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {  in cpg_mssr_suspend_noirq()
899 		if (priv->smstpcr_saved[reg].mask)  in cpg_mssr_suspend_noirq()
900 			priv->smstpcr_saved[reg].val =  in cpg_mssr_suspend_noirq()
901 				priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?  in cpg_mssr_suspend_noirq()
902 				readb(priv->base + priv->control_regs[reg]) :  in cpg_mssr_suspend_noirq()
903 				readl(priv->base + priv->control_regs[reg]);  in cpg_mssr_suspend_noirq()
907 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);  in cpg_mssr_suspend_noirq()
924 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);  in cpg_mssr_resume_noirq()
927 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {  in cpg_mssr_resume_noirq()
928 		mask = priv->smstpcr_saved[reg].mask;  in cpg_mssr_resume_noirq()
932 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)  in cpg_mssr_resume_noirq()
933 			oldval = readb(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
935 			oldval = readl(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
937 		newval |= priv->smstpcr_saved[reg].val & mask;  in cpg_mssr_resume_noirq()
941 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {  in cpg_mssr_resume_noirq()
942 			writeb(newval, priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
944 			readb(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
945 			barrier_data(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
948 			writel(newval, priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
951 		mask &= ~priv->smstpcr_saved[reg].val;  in cpg_mssr_resume_noirq()
955 		error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg],  in cpg_mssr_resume_noirq()
976 	kfree(priv->reserved_ids);  in cpg_mssr_reserved_exit()
990 	 * to a non-Linux system will be disabled when Linux is booted.  in cpg_mssr_reserved_init()
992 	 * To avoid such situation, renesas-cpg-mssr assumes the device which has  in cpg_mssr_reserved_init()
993 	 * status = "reserved" is assigned to a non-Linux system, and adds CLK_IGNORE_UNUSED flag  in cpg_mssr_reserved_init()
1000 	 * =>		clocks = <&cpg CPG_MOD 202>,  in cpg_mssr_reserved_init()
1001 	 *			 <&cpg CPG_CORE R8A7795_CLK_S3D1>,  in cpg_mssr_reserved_init()
1011 		of_for_each_phandle(&it, rc, node, "clocks", "#clock-cells", -1) {  in cpg_mssr_reserved_init()
1014 			if (it.node != priv->np)  in cpg_mssr_reserved_init()
1026 				return -ENOMEM;  in cpg_mssr_reserved_init()
1029 			if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)  in cpg_mssr_reserved_init()
1034 			ids[num] = info->num_total_core_clks + idx;  in cpg_mssr_reserved_init()
1040 	priv->num_reserved_ids	= num;  in cpg_mssr_reserved_init()
1041 	priv->reserved_ids	= ids;  in cpg_mssr_reserved_init()
1054 	if (info->init) {  in cpg_mssr_common_init()
1055 		error = info->init(dev);  in cpg_mssr_common_init()
1060 	nclks = info->num_total_core_clks + info->num_hw_mod_clks;  in cpg_mssr_common_init()
1063 		return -ENOMEM;  in cpg_mssr_common_init()
1065 	priv->np = np;  in cpg_mssr_common_init()
1066 	priv->dev = dev;  in cpg_mssr_common_init()
1067 	spin_lock_init(&priv->rmw_lock);  in cpg_mssr_common_init()
1069 	priv->base = of_iomap(np, 0);  in cpg_mssr_common_init()
1070 	if (!priv->base) {  in cpg_mssr_common_init()
1071 		error = -ENOMEM;  in cpg_mssr_common_init()
1075 	priv->num_core_clks = info->num_total_core_clks;  in cpg_mssr_common_init()
1076 	priv->num_mod_clks = info->num_hw_mod_clks;  in cpg_mssr_common_init()
1077 	priv->last_dt_core_clk = info->last_dt_core_clk;  in cpg_mssr_common_init()
1078 	RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);  in cpg_mssr_common_init()
1079 	priv->reg_layout = info->reg_layout;  in cpg_mssr_common_init()
1080 	if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {  in cpg_mssr_common_init()
1081 		priv->status_regs = mstpsr;  in cpg_mssr_common_init()
1082 		priv->control_regs = smstpcr;  in cpg_mssr_common_init()
1083 		priv->reset_regs = srcr;  in cpg_mssr_common_init()
1084 		priv->reset_clear_regs = srstclr;  in cpg_mssr_common_init()
1085 	} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {  in cpg_mssr_common_init()
1086 		priv->control_regs = stbcr;  in cpg_mssr_common_init()
1087 	} else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {  in cpg_mssr_common_init()
1088 		priv->status_regs = mstpsr_for_gen4;  in cpg_mssr_common_init()
1089 		priv->control_regs = mstpcr_for_gen4;  in cpg_mssr_common_init()
1090 		priv->reset_regs = srcr_for_gen4;  in cpg_mssr_common_init()
1091 		priv->reset_clear_regs = srstclr_for_gen4;  in cpg_mssr_common_init()
1093 		error = -EINVAL;  in cpg_mssr_common_init()
1098 		priv->clks[i] = ERR_PTR(-ENOENT);  in cpg_mssr_common_init()
1115 	if (priv->base)  in cpg_mssr_common_init()
1116 		iounmap(priv->base);  in cpg_mssr_common_init()
1132 	for (i = 0; i < info->num_early_core_clks; i++)  in cpg_mssr_early_init()
1133 		cpg_mssr_register_core_clk(&info->early_core_clks[i], info,  in cpg_mssr_early_init()
1136 	for (i = 0; i < info->num_early_mod_clks; i++)  in cpg_mssr_early_init()
1137 		cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,  in cpg_mssr_early_init()
1144 	struct device *dev = &pdev->dev;  in cpg_mssr_probe()
1145 	struct device_node *np = dev->of_node;  in cpg_mssr_probe()
1154 		error = cpg_mssr_common_init(dev, dev->of_node, info);  in cpg_mssr_probe()
1160 	priv->dev = dev;  in cpg_mssr_probe()
1163 	for (i = 0; i < info->num_core_clks; i++)  in cpg_mssr_probe()
1164 		cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);  in cpg_mssr_probe()
1166 	for (i = 0; i < info->num_mod_clks; i++)  in cpg_mssr_probe()
1167 		cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);  in cpg_mssr_probe()
1175 	error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,  in cpg_mssr_probe()
1176 					info->num_core_pm_clks);  in cpg_mssr_probe()
1181 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)  in cpg_mssr_probe()
1194 		.name	= "renesas-cpg-mssr",
1220 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");