Lines Matching +full:0 +full:x8c8

31 #define CPG_PLLECR		0x0820	/* PLL Enable Control Register */
36 #define CPG_PLL1CR0		0x830	/* PLLn Control Registers */
37 #define CPG_PLL1CR1		0x8b0
38 #define CPG_PLL2CR0		0x834
39 #define CPG_PLL2CR1		0x8b8
40 #define CPG_PLL3CR0		0x83c
41 #define CPG_PLL3CR1		0x8c0
42 #define CPG_PLL4CR0		0x844
43 #define CPG_PLL4CR1		0x8c8
44 #define CPG_PLL6CR0		0x84c
45 #define CPG_PLL6CR1		0x8d8
53 #define CPG_PLLxCR0_SSDEPT	GENMASK(6, 0)	/* SSCG Modulation Depth */
57 #define CPG_PLLxCR1_NF25	GENMASK(24, 0)	/* Fractional mult. factor */
61 #define CPG_PLLxCR1_NF24	GENMASK(23, 0)	/* Fractional mult. factor */
65 #define CPG_RPCCKCR		0x874	/* RPC Clock Freq. Control Register */
67 #define CPG_SD0CKCR1		0x8a4	/* SD-IF0 Clock Freq. Control Reg. 1 */
118 			nf = 0;  in cpg_pll_8_25_clk_determine_rate()
127 		nf = 0;  in cpg_pll_8_25_clk_determine_rate()
131 	return 0;  in cpg_pll_8_25_clk_determine_rate()
147 			nf = 0;  in cpg_pll_8_25_clk_set_rate()
171 	cpg_reg_modify(pll_clk->pllcr0_reg, 0, CPG_PLLxCR0_KICK);  in cpg_pll_8_25_clk_set_rate()
183 				  val & pll_clk->pllecr_pllst_mask, 0, 1000);  in cpg_pll_8_25_clk_set_rate()
262 #define CPG_FRQCRB			0x00000804
264 #define CPG_FRQCRC0			0x00000808
265 #define CPG_FRQCRC1			0x000008e0
320 	return 0;  in cpg_z_clk_determine_rate()
343 	cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);  in cpg_z_clk_set_rate()
356 			return 0;  in cpg_z_clk_set_rate()
416 	{ 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
429 	parent = clks[core->parent & 0xffff];	/* some types use high bits */  in rcar_gen4_cpg_clk_register()
494 			div = core->div & 0xffff;  in rcar_gen4_cpg_clk_register()
513 						  __clk_get_name(parent), 0,  in rcar_gen4_cpg_clk_register()
514 						  base + CPG_RPCCKCR, 3, 2, 0,  in rcar_gen4_cpg_clk_register()
531 					 __clk_get_name(parent), 0, mult, div);  in rcar_gen4_cpg_clk_register()
541 	return 0;  in rcar_gen4_cpg_init()