Lines Matching +full:8 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
55 {3, 8},
68 {2, 8},
91 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
121 BUS_MSTOP(3, BIT(5))),
123 BUS_MSTOP(5, BIT(10))),
125 BUS_MSTOP(5, BIT(11))),
127 BUS_MSTOP(2, BIT(13))),
129 BUS_MSTOP(2, BIT(14))),
131 BUS_MSTOP(11, BIT(13))),
132 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
133 BUS_MSTOP(11, BIT(14))),
135 BUS_MSTOP(11, BIT(15))),
137 BUS_MSTOP(12, BIT(0))),
139 BUS_MSTOP(3, BIT(10))),
141 BUS_MSTOP(3, BIT(10))),
143 BUS_MSTOP(1, BIT(0))),
145 BUS_MSTOP(1, BIT(0))),
147 BUS_MSTOP(5, BIT(12))),
149 BUS_MSTOP(5, BIT(12))),
151 BUS_MSTOP(5, BIT(13))),
153 BUS_MSTOP(5, BIT(13))),
154 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
155 BUS_MSTOP(3, BIT(14))),
157 BUS_MSTOP(3, BIT(13))),
159 BUS_MSTOP(1, BIT(1))),
161 BUS_MSTOP(1, BIT(2))),
163 BUS_MSTOP(1, BIT(3))),
165 BUS_MSTOP(1, BIT(4))),
166 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
167 BUS_MSTOP(1, BIT(5))),
169 BUS_MSTOP(1, BIT(6))),
171 BUS_MSTOP(1, BIT(7))),
173 BUS_MSTOP(1, BIT(8))),
175 BUS_MSTOP(8, BIT(2))),
177 BUS_MSTOP(8, BIT(2))),
179 BUS_MSTOP(8, BIT(2))),
181 BUS_MSTOP(8, BIT(2))),
183 BUS_MSTOP(8, BIT(3))),
184 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
185 BUS_MSTOP(8, BIT(3))),
187 BUS_MSTOP(8, BIT(3))),
189 BUS_MSTOP(8, BIT(3))),
191 BUS_MSTOP(8, BIT(4))),
193 BUS_MSTOP(8, BIT(4))),
195 BUS_MSTOP(8, BIT(4))),
197 BUS_MSTOP(8, BIT(4))),
199 BUS_MSTOP(9, BIT(4))),
201 BUS_MSTOP(9, BIT(4))),
203 BUS_MSTOP(9, BIT(4))),
205 BUS_MSTOP(9, BIT(5))),
207 BUS_MSTOP(9, BIT(5))),
209 BUS_MSTOP(9, BIT(5))),
210 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
211 BUS_MSTOP(9, BIT(6))),
213 BUS_MSTOP(9, BIT(6))),
215 BUS_MSTOP(9, BIT(6))),
217 BUS_MSTOP(9, BIT(7))),
219 BUS_MSTOP(9, BIT(7))),
221 BUS_MSTOP(9, BIT(7))),
227 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
239 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
240 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
242 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
252 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
257 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */