Lines Matching +full:6 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
121 BUS_MSTOP(3, BIT(5))),
123 BUS_MSTOP(5, BIT(10))),
125 BUS_MSTOP(5, BIT(11))),
127 BUS_MSTOP(2, BIT(13))),
128 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
129 BUS_MSTOP(2, BIT(14))),
131 BUS_MSTOP(11, BIT(13))),
133 BUS_MSTOP(11, BIT(14))),
135 BUS_MSTOP(11, BIT(15))),
137 BUS_MSTOP(12, BIT(0))),
139 BUS_MSTOP(3, BIT(10))),
141 BUS_MSTOP(3, BIT(10))),
143 BUS_MSTOP(1, BIT(0))),
145 BUS_MSTOP(1, BIT(0))),
147 BUS_MSTOP(5, BIT(12))),
149 BUS_MSTOP(5, BIT(12))),
151 BUS_MSTOP(5, BIT(13))),
153 BUS_MSTOP(5, BIT(13))),
155 BUS_MSTOP(3, BIT(14))),
157 BUS_MSTOP(3, BIT(13))),
159 BUS_MSTOP(1, BIT(1))),
161 BUS_MSTOP(1, BIT(2))),
162 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
163 BUS_MSTOP(1, BIT(3))),
165 BUS_MSTOP(1, BIT(4))),
167 BUS_MSTOP(1, BIT(5))),
169 BUS_MSTOP(1, BIT(6))),
171 BUS_MSTOP(1, BIT(7))),
173 BUS_MSTOP(1, BIT(8))),
175 BUS_MSTOP(8, BIT(2))),
177 BUS_MSTOP(8, BIT(2))),
179 BUS_MSTOP(8, BIT(2))),
180 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
181 BUS_MSTOP(8, BIT(2))),
183 BUS_MSTOP(8, BIT(3))),
185 BUS_MSTOP(8, BIT(3))),
187 BUS_MSTOP(8, BIT(3))),
189 BUS_MSTOP(8, BIT(3))),
191 BUS_MSTOP(8, BIT(4))),
193 BUS_MSTOP(8, BIT(4))),
195 BUS_MSTOP(8, BIT(4))),
197 BUS_MSTOP(8, BIT(4))),
198 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
199 BUS_MSTOP(9, BIT(4))),
200 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
201 BUS_MSTOP(9, BIT(4))),
202 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
203 BUS_MSTOP(9, BIT(4))),
204 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
205 BUS_MSTOP(9, BIT(5))),
206 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
207 BUS_MSTOP(9, BIT(5))),
208 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
209 BUS_MSTOP(9, BIT(5))),
210 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
211 BUS_MSTOP(9, BIT(6))),
212 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
213 BUS_MSTOP(9, BIT(6))),
214 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
215 BUS_MSTOP(9, BIT(6))),
216 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
217 BUS_MSTOP(9, BIT(7))),
218 DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28,
219 BUS_MSTOP(9, BIT(7))),
220 DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
221 BUS_MSTOP(9, BIT(7))),
226 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
229 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
230 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
231 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
237 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
238 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
241 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
255 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
264 DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */
265 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */