Lines Matching +full:4 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
54 {2, 4},
61 {1, 4},
67 {1, 4},
70 {4, 64},
96 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
121 BUS_MSTOP(3, BIT(5))),
122 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
123 BUS_MSTOP(5, BIT(10))),
124 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
125 BUS_MSTOP(5, BIT(11))),
126 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
127 BUS_MSTOP(2, BIT(13))),
128 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
129 BUS_MSTOP(2, BIT(14))),
130 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
131 BUS_MSTOP(11, BIT(13))),
132 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
133 BUS_MSTOP(11, BIT(14))),
134 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
135 BUS_MSTOP(11, BIT(15))),
136 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
137 BUS_MSTOP(12, BIT(0))),
138 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
139 BUS_MSTOP(3, BIT(10))),
140 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
141 BUS_MSTOP(3, BIT(10))),
142 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
143 BUS_MSTOP(1, BIT(0))),
144 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
145 BUS_MSTOP(1, BIT(0))),
146 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
147 BUS_MSTOP(5, BIT(12))),
149 BUS_MSTOP(5, BIT(12))),
151 BUS_MSTOP(5, BIT(13))),
153 BUS_MSTOP(5, BIT(13))),
154 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
155 BUS_MSTOP(3, BIT(14))),
156 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
157 BUS_MSTOP(3, BIT(13))),
158 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
159 BUS_MSTOP(1, BIT(1))),
160 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
161 BUS_MSTOP(1, BIT(2))),
162 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
163 BUS_MSTOP(1, BIT(3))),
164 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
165 BUS_MSTOP(1, BIT(4))),
166 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
167 BUS_MSTOP(1, BIT(5))),
168 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
169 BUS_MSTOP(1, BIT(6))),
170 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
171 BUS_MSTOP(1, BIT(7))),
172 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
173 BUS_MSTOP(1, BIT(8))),
175 BUS_MSTOP(8, BIT(2))),
176 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
177 BUS_MSTOP(8, BIT(2))),
179 BUS_MSTOP(8, BIT(2))),
181 BUS_MSTOP(8, BIT(2))),
183 BUS_MSTOP(8, BIT(3))),
185 BUS_MSTOP(8, BIT(3))),
187 BUS_MSTOP(8, BIT(3))),
189 BUS_MSTOP(8, BIT(3))),
191 BUS_MSTOP(8, BIT(4))),
193 BUS_MSTOP(8, BIT(4))),
195 BUS_MSTOP(8, BIT(4))),
197 BUS_MSTOP(8, BIT(4))),
199 BUS_MSTOP(9, BIT(4))),
201 BUS_MSTOP(9, BIT(4))),
202 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
203 BUS_MSTOP(9, BIT(4))),
205 BUS_MSTOP(9, BIT(5))),
207 BUS_MSTOP(9, BIT(5))),
209 BUS_MSTOP(9, BIT(5))),
211 BUS_MSTOP(9, BIT(6))),
213 BUS_MSTOP(9, BIT(6))),
215 BUS_MSTOP(9, BIT(6))),
217 BUS_MSTOP(9, BIT(7))),
219 BUS_MSTOP(9, BIT(7))),
221 BUS_MSTOP(9, BIT(7))),
235 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
236 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
241 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
242 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
243 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
244 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
245 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
246 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
247 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
248 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
249 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
250 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
251 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
252 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
253 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */