Lines Matching +full:4 +full:- +full:6
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
54 {2, 4},
61 {1, 4},
67 {1, 4},
70 {4, 64},
96 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
122 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
124 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
126 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
128 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
130 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
132 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
134 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
136 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
138 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
140 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
142 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
144 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
146 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
154 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
156 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
158 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
160 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
162 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
164 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
165 BUS_MSTOP(1, BIT(4))),
166 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
168 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
169 BUS_MSTOP(1, BIT(6))),
170 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
172 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
176 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
180 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
191 BUS_MSTOP(8, BIT(4))),
193 BUS_MSTOP(8, BIT(4))),
195 BUS_MSTOP(8, BIT(4))),
197 BUS_MSTOP(8, BIT(4))),
198 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
199 BUS_MSTOP(9, BIT(4))),
200 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
201 BUS_MSTOP(9, BIT(4))),
202 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
203 BUS_MSTOP(9, BIT(4))),
204 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
206 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
208 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
210 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
211 BUS_MSTOP(9, BIT(6))),
212 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
213 BUS_MSTOP(9, BIT(6))),
214 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
215 BUS_MSTOP(9, BIT(6))),
216 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
218 DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28,
220 DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
226 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
229 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
230 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
231 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
235 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
236 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
237 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
238 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
241 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
242 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
243 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
244 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
245 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
246 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
247 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
248 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
249 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
250 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
251 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
252 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
253 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
255 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
264 DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */
265 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */