Lines Matching +full:12 +full:- +full:13
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
127 BUS_MSTOP(2, BIT(13))),
131 BUS_MSTOP(11, BIT(13))),
137 BUS_MSTOP(12, BIT(0))),
140 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
142 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
147 BUS_MSTOP(5, BIT(12))),
149 BUS_MSTOP(5, BIT(12))),
151 BUS_MSTOP(5, BIT(13))),
153 BUS_MSTOP(5, BIT(13))),
157 BUS_MSTOP(3, BIT(13))),
192 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
194 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
198 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
200 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
202 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
204 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
206 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
208 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
210 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
212 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
214 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
216 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
218 DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28,
220 DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
229 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
245 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
246 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
247 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
254 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
255 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
256 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
257 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
258 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
259 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
260 DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */
261 DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */
262 DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */
263 DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */
264 DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */
265 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */