Lines Matching +full:10 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
121 BUS_MSTOP(3, BIT(5))),
123 BUS_MSTOP(5, BIT(10))),
125 BUS_MSTOP(5, BIT(11))),
127 BUS_MSTOP(2, BIT(13))),
129 BUS_MSTOP(2, BIT(14))),
131 BUS_MSTOP(11, BIT(13))),
133 BUS_MSTOP(11, BIT(14))),
135 BUS_MSTOP(11, BIT(15))),
136 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
137 BUS_MSTOP(12, BIT(0))),
139 BUS_MSTOP(3, BIT(10))),
141 BUS_MSTOP(3, BIT(10))),
143 BUS_MSTOP(1, BIT(0))),
145 BUS_MSTOP(1, BIT(0))),
147 BUS_MSTOP(5, BIT(12))),
149 BUS_MSTOP(5, BIT(12))),
151 BUS_MSTOP(5, BIT(13))),
153 BUS_MSTOP(5, BIT(13))),
155 BUS_MSTOP(3, BIT(14))),
157 BUS_MSTOP(3, BIT(13))),
159 BUS_MSTOP(1, BIT(1))),
161 BUS_MSTOP(1, BIT(2))),
163 BUS_MSTOP(1, BIT(3))),
165 BUS_MSTOP(1, BIT(4))),
167 BUS_MSTOP(1, BIT(5))),
169 BUS_MSTOP(1, BIT(6))),
170 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
171 BUS_MSTOP(1, BIT(7))),
173 BUS_MSTOP(1, BIT(8))),
174 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
175 BUS_MSTOP(8, BIT(2))),
176 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
177 BUS_MSTOP(8, BIT(2))),
178 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
179 BUS_MSTOP(8, BIT(2))),
180 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
181 BUS_MSTOP(8, BIT(2))),
182 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
183 BUS_MSTOP(8, BIT(3))),
184 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
185 BUS_MSTOP(8, BIT(3))),
186 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
187 BUS_MSTOP(8, BIT(3))),
188 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
189 BUS_MSTOP(8, BIT(3))),
190 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
191 BUS_MSTOP(8, BIT(4))),
192 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
193 BUS_MSTOP(8, BIT(4))),
194 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
195 BUS_MSTOP(8, BIT(4))),
196 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
197 BUS_MSTOP(8, BIT(4))),
199 BUS_MSTOP(9, BIT(4))),
201 BUS_MSTOP(9, BIT(4))),
203 BUS_MSTOP(9, BIT(4))),
205 BUS_MSTOP(9, BIT(5))),
207 BUS_MSTOP(9, BIT(5))),
209 BUS_MSTOP(9, BIT(5))),
211 BUS_MSTOP(9, BIT(6))),
213 BUS_MSTOP(9, BIT(6))),
214 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
215 BUS_MSTOP(9, BIT(6))),
217 BUS_MSTOP(9, BIT(7))),
219 BUS_MSTOP(9, BIT(7))),
221 BUS_MSTOP(9, BIT(7))),
228 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
243 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
244 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
250 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
251 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
252 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
253 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
259 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */